A 700mV low power pipeline ADC using a novel common mode feedback circuit and offset cancellation technique

Abstract

An 8 bit, 1.5 b/stage fully differential (FD) multiplying digital to analog converter (MDAC) pipeline ADC for use in a smart RFID is presented in this paper. The FD Operational Transconductance Amplifier (OTA) in the MDAC utilizes a novel common mode (CM) amplifier, which is inherently stable demonstrating reduced common mode offset and improved compensation tracking across process. Furthermore, a simple offset cancellation technique robust to device leakage is introduced to correct error due to leakage induced input offset voltage drift. Monte Carlo simulation results show that for the input voltage range of ±400mV, ADC can achieve 8 ENOB with sampling frequency at 16 kHz. Total ADC power consumption is 5.1uA with 0.7V power supply. The ADC was submitted for fabrication in 180nm CMOS with results forth coming.