{"title":"An ultra-low frequency ring oscillator with programmable tracking using a phase-locked loop","authors":"Tsung-Hsueh Lee, P. Abshire","doi":"10.1109/MWSCAS.2012.6291946","DOIUrl":null,"url":null,"abstract":"This paper presents a programmable ultra-low frequency ring oscillator designed in a 0.5μm CMOS technology with 3.3 V power supply. In normal operation, the oscillator produces a periodic signal without external inputs (other than power and ground). During programming, the oscillator tracks and memorizes the input reference frequency using a phase-locked loop (PLL) architecture. The PLL controls an on-chip nonvolatile memory using a floating gate structure; the voltage on the floating gate node is applied to the voltage-controlled oscillator (VCO) to generate the desired frequency. A high-voltage NMOS is introduced to realize the floating gate control; measurement results show that the breakdown voltage is close to 40 V. Transient simulations indicate that the circuit successfully tracks a desired frequency with maximum period jitter of 0.49 μs at the VCO output which translates to frequency error of 0.88 % at the system output.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2012.6291946","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
This paper presents a programmable ultra-low frequency ring oscillator designed in a 0.5μm CMOS technology with 3.3 V power supply. In normal operation, the oscillator produces a periodic signal without external inputs (other than power and ground). During programming, the oscillator tracks and memorizes the input reference frequency using a phase-locked loop (PLL) architecture. The PLL controls an on-chip nonvolatile memory using a floating gate structure; the voltage on the floating gate node is applied to the voltage-controlled oscillator (VCO) to generate the desired frequency. A high-voltage NMOS is introduced to realize the floating gate control; measurement results show that the breakdown voltage is close to 40 V. Transient simulations indicate that the circuit successfully tracks a desired frequency with maximum period jitter of 0.49 μs at the VCO output which translates to frequency error of 0.88 % at the system output.