一种超低频环形振荡器,采用锁相环进行可编程跟踪

Tsung-Hsueh Lee, P. Abshire
{"title":"一种超低频环形振荡器,采用锁相环进行可编程跟踪","authors":"Tsung-Hsueh Lee, P. Abshire","doi":"10.1109/MWSCAS.2012.6291946","DOIUrl":null,"url":null,"abstract":"This paper presents a programmable ultra-low frequency ring oscillator designed in a 0.5μm CMOS technology with 3.3 V power supply. In normal operation, the oscillator produces a periodic signal without external inputs (other than power and ground). During programming, the oscillator tracks and memorizes the input reference frequency using a phase-locked loop (PLL) architecture. The PLL controls an on-chip nonvolatile memory using a floating gate structure; the voltage on the floating gate node is applied to the voltage-controlled oscillator (VCO) to generate the desired frequency. A high-voltage NMOS is introduced to realize the floating gate control; measurement results show that the breakdown voltage is close to 40 V. Transient simulations indicate that the circuit successfully tracks a desired frequency with maximum period jitter of 0.49 μs at the VCO output which translates to frequency error of 0.88 % at the system output.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"An ultra-low frequency ring oscillator with programmable tracking using a phase-locked loop\",\"authors\":\"Tsung-Hsueh Lee, P. Abshire\",\"doi\":\"10.1109/MWSCAS.2012.6291946\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a programmable ultra-low frequency ring oscillator designed in a 0.5μm CMOS technology with 3.3 V power supply. In normal operation, the oscillator produces a periodic signal without external inputs (other than power and ground). During programming, the oscillator tracks and memorizes the input reference frequency using a phase-locked loop (PLL) architecture. The PLL controls an on-chip nonvolatile memory using a floating gate structure; the voltage on the floating gate node is applied to the voltage-controlled oscillator (VCO) to generate the desired frequency. A high-voltage NMOS is introduced to realize the floating gate control; measurement results show that the breakdown voltage is close to 40 V. Transient simulations indicate that the circuit successfully tracks a desired frequency with maximum period jitter of 0.49 μs at the VCO output which translates to frequency error of 0.88 % at the system output.\",\"PeriodicalId\":324891,\"journal\":{\"name\":\"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)\",\"volume\":\"61 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-09-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MWSCAS.2012.6291946\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2012.6291946","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3

摘要

本文提出了一种采用0.5μm CMOS工艺、3.3 V电源的可编程超低频环形振荡器。在正常工作中,振荡器在没有外部输入(除了电源和地)的情况下产生周期信号。在编程过程中,振荡器使用锁相环(PLL)结构跟踪和存储输入参考频率。锁相环采用浮栅结构控制片上非易失性存储器;浮栅节点上的电压被施加到压控振荡器(VCO)上,以产生所需的频率。采用高压NMOS实现浮栅控制;测量结果表明,击穿电压接近40 V。瞬态仿真表明,该电路成功地跟踪了一个期望的频率,在VCO输出处最大周期抖动为0.49 μs,在系统输出处频率误差为0.88%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
An ultra-low frequency ring oscillator with programmable tracking using a phase-locked loop
This paper presents a programmable ultra-low frequency ring oscillator designed in a 0.5μm CMOS technology with 3.3 V power supply. In normal operation, the oscillator produces a periodic signal without external inputs (other than power and ground). During programming, the oscillator tracks and memorizes the input reference frequency using a phase-locked loop (PLL) architecture. The PLL controls an on-chip nonvolatile memory using a floating gate structure; the voltage on the floating gate node is applied to the voltage-controlled oscillator (VCO) to generate the desired frequency. A high-voltage NMOS is introduced to realize the floating gate control; measurement results show that the breakdown voltage is close to 40 V. Transient simulations indicate that the circuit successfully tracks a desired frequency with maximum period jitter of 0.49 μs at the VCO output which translates to frequency error of 0.88 % at the system output.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信