A novel PR channelizer-based architecture for estimation and correction of timing and gain mismatches in two channel TI-ADCs

Abstract

In this paper we present a novel architecture for estimating and correcting time and gain mismatches in a two channel time-interleaved analog-to-digital converter (TI-ADC) which is embedded in a digital communication receiver. TI-ADCs can offer a significant increase in the sample rate however their usage is limited due to the fact that their performance is strongly degraded by timing and gain mismatches between the channels. A standard mismatches estimation approach requires the inclusion of a pilot tone between the signal spectrum and DC. As an effect of the mismatches the aliased copy of the low frequency pilot tone shows up at high frequency where it is processed through an high-pass filter and used for the estimation. After the mismatches cancellation has been performed the low frequency pilot tone needs to be removed from the `clean' signal spectrum which also needs be down converted to base-band. After the down conversion the sample rate has to be adjusted to be commensurate to the new reduced signal bandwidth. Modern software defined radio architectures are based on perfect reconstruction (PR) up and down converter channelizers. In this paper we present a novel architecture for estimating time and gain mismatches in two channel TI-ADCs which is based on PR channelizers and can be naturally embedded in modern digital radio receiver architectures. The PR polyphase channelizer engines provide us a compact and unique solution for filtering the aliased high frequency tone which is used for the mismatch estimation, canceling the low frequency tone and for down converting the corrected signal spectrum to base-band while adjusting its sample rate to the reduced bandwidth.