2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)最新文献

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Optimization of placement solutions for routability 可达性布局方案的优化
2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2013-05-29 DOI: 10.1145/2463209.2488923
Wen-Hao Liu, Cheng-Kok Koh, Yih-Lang Li
{"title":"Optimization of placement solutions for routability","authors":"Wen-Hao Liu, Cheng-Kok Koh, Yih-Lang Li","doi":"10.1145/2463209.2488923","DOIUrl":"https://doi.org/10.1145/2463209.2488923","url":null,"abstract":"Routability has become a critical issue in VLSI design flow. To avoid producing an unroutable design, many placers [47] invoke global routers to get a congestion map and then move cells to reduce congestion based on this map. However, as cells move, the accuracy of the congestion map degrades, thereby affecting the effectiveness of the placer in minimizing congestions. Moreover, most global routers [8-13] ignore local congestion. If placers are guided by these routers, it may produce hard-to-route placement solutions in terms of detailed routing. This work develops a routability optimizer, called Ropt, to reduce both global and local routing congestion levels of a given placement. Based on a local-routability-aware routing model, Ropt builds a global routing instance to obtain global and local congestion information for guiding global re-placement. In addition, this work presents a new legalization scheme to preserve the global routing instance after legalization. Finally, local detailed placement further minimizes the local congestion and wirelength. For the evaluation of Ropt, we use an academic global router and a commercial router to obtain both global and detailed routing results, respectively. Experimental results reveal that Ropt can improve the routing quality (in terms of congestion, wirelength, and violation) and routing runtime of a given placement solution.","PeriodicalId":320207,"journal":{"name":"2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123231632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
Pareto epsilon-dominance and identifiable solutions for BioCAD modeling Pareto - epsilon-dominance和BioCAD建模的可识别解
2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2013-05-29 DOI: 10.1145/2463209.2488787
C. Angione, Jole Costanza, Giovanni Carapezza, P. Lio’, Giuseppe Nicosia
{"title":"Pareto epsilon-dominance and identifiable solutions for BioCAD modeling","authors":"C. Angione, Jole Costanza, Giovanni Carapezza, P. Lio’, Giuseppe Nicosia","doi":"10.1145/2463209.2488787","DOIUrl":"https://doi.org/10.1145/2463209.2488787","url":null,"abstract":"We propose a framework to design metabolic pathways in which many objectives are optimized simultaneously. This allows to characterize the energy signature in models of algal and mitochondrial metabolism. The optimal design and assessment of the model is achieved through a multi-objective optimization technique driven by epsilon-dominance and identifiability analysis. A faster convergence process with robust candidate solutions is permitted by a relaxed Pareto dominance, regulating the granularity of the approximation of the Pareto front. Our framework is also suitable for black-box analysis, enabling to investigate and optimize any biological pathway modeled with ODEs, DAEs, FBA and GPR.","PeriodicalId":320207,"journal":{"name":"2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115249467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Predicting future technology performance 预测未来技术性能
2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2013-05-29 DOI: 10.1145/2463209.2488774
A. Asenov, C. Alexander, C. Riddet, E. Towie
{"title":"Predicting future technology performance","authors":"A. Asenov, C. Alexander, C. Riddet, E. Towie","doi":"10.1145/2463209.2488774","DOIUrl":"https://doi.org/10.1145/2463209.2488774","url":null,"abstract":"In this paper we highlight the important role of full-scale 3D Ensemble Monte Carlo (EMC) transport simulations in the performance analysis of contemporary and future decananometer MOSFETs. Considering both electron and hole transport in alternative device structures and materials we demonstrate that conventional drift diffusion (DD) simulations using standard mobility models fail to capture the non-equilibrium transport effects present in these devices, limiting their effectiveness in terms of performing predictive simulation of Si based FinFETs. We clearly demonstrate the capabilities and the power of EMC in evaluating the scaling potential and performance of FinFETs and quantum well transistors employing high mobility materials and the impact that additional scattering sources has on their performance.","PeriodicalId":320207,"journal":{"name":"2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131032823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Hybrid energy storage systems and battery management for electric vehicles 电动汽车的混合能源存储系统和电池管理
2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2013-05-29 DOI: 10.1145/2463209.2488854
Sangyoung Park, Younghyun Kim, N. Chang
{"title":"Hybrid energy storage systems and battery management for electric vehicles","authors":"Sangyoung Park, Younghyun Kim, N. Chang","doi":"10.1145/2463209.2488854","DOIUrl":"https://doi.org/10.1145/2463209.2488854","url":null,"abstract":"Electric vehicles (EV) are considered as a strong alternative of internal combustion engine vehicles expecting lower carbon emission. However, their actual benefits are not yet clearly verified while the energy efficiency can be improved in many ways. The carbon emission benefits from EV is largely diminished if we charge EV with electricity from petroleum power plants due to power loss during generation, transmission, conversion and charging. On the other hand, regenerative braking is direct power conversion from the wheel to battery and one of the most important processes that can enhance energy efficiency of EV. Power loss during regenerative braking can be reduced by hybrid energy storage system (HESS) such that super-capacitors accept high power as batteries have small rate capability. Conventional charge management does not systematically exchange charge between the supercapacitor and battery. However, asymmetry in acceleration and deceleration as well as battery charging and discharging capability make the supercapacitor state of charge (SoC) management override the efficiency optimization. Unlike previous works, we show how charge migration during idle and cruise/stopping time can be beneficial in terms of energy efficiency and cruise range. Systematic charge migration decouples SoC management and charging efficiency optimization giving a higher degree of freedom to charging efficiency optimization. We demonstrate the proposed charge migration between the supercapacitor and battery improves energy efficiency by 19.4%.","PeriodicalId":320207,"journal":{"name":"2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131044384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 50
Scalable vectorless power grid current integrity verification 可伸缩的无矢量电网电流完整性验证
2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2013-05-29 DOI: 10.1145/2463209.2488840
Zhuo Feng
{"title":"Scalable vectorless power grid current integrity verification","authors":"Zhuo Feng","doi":"10.1145/2463209.2488840","DOIUrl":"https://doi.org/10.1145/2463209.2488840","url":null,"abstract":"To deal with the growing phenomenon of electromigration (EM), power grid current integrity verification becomes indispensable to designing reliable power delivery networks (PDNs). Unlike previous works that focus on vectorless voltage integrity verification of power grids, in this work, for the first time we present a scalable vectorless power grid current integrity verification framework. By taking advantage of multilevel power grid verifications, large-scale power grid current integrity verification tasks can be achieved in a very efficient way. Additionally, a novel EM-aware geometric power grid reduction method is proposed to well preserve the similar geometric and electrical properties of the original grid on the coarse-level power grids, which allows to quickly identify the potential “hot wires” that may carry greater-than-desired currents in a given power grid design. The proposed multilevel power grid verification algorithm provides flexible tradeoffs between the current integrity verification cost and solution quality, while the desired upper/lower bounds for worst case currents flowing through a wire can also be computed efficiently. Extensive experimental results show that our current integrity verification approach can efficiently handle very large power grid designs with good solution quality.","PeriodicalId":320207,"journal":{"name":"2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130611904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
TinySPICE: A parallel SPICE simulator on GPU for massively repeated small circuit simulations TinySPICE: GPU上的并行SPICE模拟器,用于大规模重复的小电路模拟
2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2013-05-29 DOI: 10.1145/2463209.2488843
Lengfei Han, Xueqian Zhao, Zhuo Feng
{"title":"TinySPICE: A parallel SPICE simulator on GPU for massively repeated small circuit simulations","authors":"Lengfei Han, Xueqian Zhao, Zhuo Feng","doi":"10.1145/2463209.2488843","DOIUrl":"https://doi.org/10.1145/2463209.2488843","url":null,"abstract":"In nowadays variation-aware IC designs, cell characterizations and SRAM memory yield analysis require many thousands or even millions of repeated SPICE simulations for relatively small nonlinear circuits. In this work, we present a massively parallel SPICE simulator on GPU, TinySPICE, for efficiently analyzing small nonlinear circuits, such as standard cell designs, SRAMs, etc. In order to gain high accuracy and efficiency, we present GPU-based parametric three-dimensional (3D) LUTs for fast device evaluations. A series of GPU-friendly data structures and algorithm flows have been proposed in TinySPICE to fully utilize the GPU hardware resources, and minimize data communications between the GPU and CPU. Our GPU implementation allows for a large number of small circuit simulations in GPU's shared memory that involves novel circuit linearization and matrix solution techniques, and eliminates most of the GPU device memory accesses during the Newton-Raphson (NR) iterations, which enables extremely high-throughput SPICE simulations on GPU. Compared with CPU-based TinySPICE simulator, GPU-based TinySPICE achieves up to 138X speedups for parametric SRAM yield analysis without loss of accuracy.","PeriodicalId":320207,"journal":{"name":"2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130669813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Low-energy encryption for medical devices: Security adds an extra design dimension 用于医疗设备的低能耗加密:安全性增加了一个额外的设计维度
2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2013-05-29 DOI: 10.1145/2463209.2488752
Junfeng Fan, Oscar Reparaz, Vladimir Rožić, I. Verbauwhede
{"title":"Low-energy encryption for medical devices: Security adds an extra design dimension","authors":"Junfeng Fan, Oscar Reparaz, Vladimir Rožić, I. Verbauwhede","doi":"10.1145/2463209.2488752","DOIUrl":"https://doi.org/10.1145/2463209.2488752","url":null,"abstract":"Smart medical devices will only be smart if they also include technology to provide security and privacy. In practice this means the inclusion of cryptographic algorithms of sufficient cryptographic strength. For battery operated devices or for passively powered devices, these cryptographic algorithms need highly efficient, low power, low energy realizations. Moreover, unique to cryptographic implementations is that they also need protection against physical tampering either active or passive. This means that countermeasures need to be included during the design process. Similar to design for low energy, design for physical protection needs to be addressed at all design abstraction levels. Differently, while skipping one optimization step in a design for low energy or low power, merely reduces the battery life time, skipping a countermeasure, means opening the door for a possible attack. Designing for security requires a thorough threat analysis and a balanced selection of countermeasures. This paper will discuss the different abstraction layers and design methods applied to obtain low power/low energy and at the same time side-channel and fault attack resistant cryptographic implementations. To provide a variety of security features, including location privacy, it is clear that medical devices need public key cryptography (PKC). It will be illustrated with the design of a low energy elliptic curve based public key programmable co-processor. It only needs 5.1μJ of energy in a 0.13 μm CMOS technology for one point multiplication and includes a selected set of countermeasures against physical attacks.","PeriodicalId":320207,"journal":{"name":"2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125374603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Automatic clustering of wafer spatial signatures 晶圆空间特征的自动聚类
2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2013-05-29 DOI: 10.1145/2463209.2488821
Wangyang Zhang, Xin Li, S. Saxena, A. Strojwas, Rob A. Rutenbar
{"title":"Automatic clustering of wafer spatial signatures","authors":"Wangyang Zhang, Xin Li, S. Saxena, A. Strojwas, Rob A. Rutenbar","doi":"10.1145/2463209.2488821","DOIUrl":"https://doi.org/10.1145/2463209.2488821","url":null,"abstract":"In this paper, we propose a methodology based on unsupervised learning for automatic clustering of wafer spatial signatures to aid yield improvement. Our proposed methodology is based on three steps. First, we apply sparse regression to automatically capture wafer spatial signatures by a small number of features. Next, we apply an unsupervised hierarchical clustering algorithm to divide wafers into a few clusters where all wafers within the same cluster are similar. Finally, we develop a modified L-method to determine the appropriate number of clusters from the hierarchical clustering result. The accuracy of the proposed methodology is demonstrated by several industrial data sets of silicon measurements.","PeriodicalId":320207,"journal":{"name":"2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"29 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123577722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
A new time-stepping method for circuit simulation 一种新的电路仿真时间步进方法
2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2013-05-29 DOI: 10.1145/2463209.2488904
G. Fang
{"title":"A new time-stepping method for circuit simulation","authors":"G. Fang","doi":"10.1145/2463209.2488904","DOIUrl":"https://doi.org/10.1145/2463209.2488904","url":null,"abstract":"Adaptive time-stepping is crucially important for the efficiency of a circuit simulator. Existing time-stepping methods rely on information at prior time point(s) to select step sizes, which can be problematic when the circuit is undergoing a fast transition. In this work, we propose a new time-stepping method that solves the circuit equations together with the condition for local truncation error (LTE) as one nonlinear system. Circuit solution and step size are obtained simultaneously for the current time point. It allows designers to have direct control of LTE so the errors can be distributed more evenly along non-uniformed time grid. Experiments show the new method generates significantly less time points and is faster for the same accuracy settings. It is also more accurate for the simulation of non-dissipative circuits.","PeriodicalId":320207,"journal":{"name":"2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123749206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Predicting future product performance: Modeling and evaluation of standard cells in FinFET technologies 预测未来产品性能:FinFET技术中标准电池的建模和评估
2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) Pub Date : 2013-05-29 DOI: 10.1145/2463209.2488775
V. Kleeberger, H. Graeb, Ulf Schlichtmann
{"title":"Predicting future product performance: Modeling and evaluation of standard cells in FinFET technologies","authors":"V. Kleeberger, H. Graeb, Ulf Schlichtmann","doi":"10.1145/2463209.2488775","DOIUrl":"https://doi.org/10.1145/2463209.2488775","url":null,"abstract":"With continued scaling of CMOS technology it becomes increasingly difficult to maintain reliable circuits. Early predictive technology and design exploration help to understand major effects of variability sources and their impact on circuit performances. With each new technology basic circuit blocks have to be redesigned to appropriately evaluate the impact of technology scaling. Therefore, this paper presents an approach which is able to find the optimal sizing of basic circuit blocks considering process variation. We utilize this approach to predict the impact of scaling in FinFET technologies and the influence of process variations in future technology nodes.","PeriodicalId":320207,"journal":{"name":"2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128149906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 49
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