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2021 35th Symposium on Microelectronics Technology and Devices (SBMicro)最新文献

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Implementation and Comparison of Algorithms for the extraction of RTN Parameters RTN参数提取算法的实现与比较
2021 35th Symposium on Microelectronics Technology and Devices (SBMicro) Pub Date : 2021-08-23 DOI: 10.1109/SBMicro50945.2021.9585757
Cláudia Theis da Silveira, Thales Exenberger Becker, Pedro Augusto Böckmann Alves, Gilson Inácio Wirth
{"title":"Implementation and Comparison of Algorithms for the extraction of RTN Parameters","authors":"Cláudia Theis da Silveira, Thales Exenberger Becker, Pedro Augusto Böckmann Alves, Gilson Inácio Wirth","doi":"10.1109/SBMicro50945.2021.9585757","DOIUrl":"https://doi.org/10.1109/SBMicro50945.2021.9585757","url":null,"abstract":"The study of noise generated internally by devices, such as the Random Telegraph Noise (RTN), provides important information about the physical and atomistic properties of micro and nanoelectronic devices, among which are Resistive Random Access Memory (ReRAM) and MOSFET. In this work, we developed two methods to extract the RTN signal parameters. The first method is an algorithm based on Hidden Markov Model (HMM), a tool widely used to analyze stochastic signals. The second method is an algorithm based on the discretization of measurements. These algorithms perform the extraction of RTN signal parameters from synthetic and experimental data measured in electronic devices, such as ReRAM and MOSFET. In addition, a comparison between the methods is carried out. Finally, by comparing the results extracted by each method, a performance analysis of both implemented algorithms, in the presence of Gaussian (white) noise is made.","PeriodicalId":318195,"journal":{"name":"2021 35th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"32 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133918286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Quantifying the Effects of Light Trapping on GaAs Solar Cells 量化光捕获对砷化镓太阳能电池的影响
2021 35th Symposium on Microelectronics Technology and Devices (SBMicro) Pub Date : 2021-08-23 DOI: 10.1109/SBMicro50945.2021.9585767
T. Borrely, Marcelo Delmondes de Lima, A. Quivy
{"title":"Quantifying the Effects of Light Trapping on GaAs Solar Cells","authors":"T. Borrely, Marcelo Delmondes de Lima, A. Quivy","doi":"10.1109/SBMicro50945.2021.9585767","DOIUrl":"https://doi.org/10.1109/SBMicro50945.2021.9585767","url":null,"abstract":"By means of numerical simulations, we have investigated the effects of generic light trapping mechanisms on conventional and impurity GaAs solar cells. Our results indicate that light-trapping mechanisms are very efficient tools for reducing the amount of material and the deposition time required to produce GaAs solar cells. We have also estimated that impurity GaAs solar cells do not benefit from light-trapping mechanisms more than conventional GaAs solar cells, unless extremely efficient light-trapping mechanisms are employed.","PeriodicalId":318195,"journal":{"name":"2021 35th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129515834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Comparative Study Between Conventional and Wave Planar Power Mosfets 常规功率场效应与波平面功率场效应的比较研究
2021 35th Symposium on Microelectronics Technology and Devices (SBMicro) Pub Date : 2021-08-23 DOI: 10.1109/SBMicro50945.2021.9585741
G. A. da Silva, S. Gimenez
{"title":"Comparative Study Between Conventional and Wave Planar Power Mosfets","authors":"G. A. da Silva, S. Gimenez","doi":"10.1109/SBMicro50945.2021.9585741","DOIUrl":"https://doi.org/10.1109/SBMicro50945.2021.9585741","url":null,"abstract":"One of most challenges of nanoelectronics area is to further increase the integration capacity and electrical performance of Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs). Several approaches have been done to reach this challenges, as for instance, the use of different fabrication processes, new transistors structures (bi and tridimensional), new materials etc. An alternative strategy, in which it is capable of reducing the total die area, mainly of the analog Complementary MOS (CMOS) integrated circuits (ICs), without affecting their electrical performance, is the use non-standard gate geometries (Diamond, Octo, Ellipsoidal, Fish, Wave etc.) for MOSFETs, instead of the rectangular one commonly used today. Previous studies have shown that by using Wave MOSFETs as a basic cell of the Planar Power MOSFETs (PPM) was able to reduce their total die areas. Therefore, the motivation of this paper is to verify by experimental data, the electrical behavior of PPM implemented with Wave layout style in relation to the one of PPM layouted with the conventional rectangular MOSFETs. The CMOS ICs technology used to manufacture these devices was of 350nm-ON Semiconductor. The main finding of this work is that the Wave MOSFET used as a base cell of a PPM (Wave PPM) present a similar electrical characteristics, but it is responsible to reduce in 9.7% its die area in comparison to the one found in PPM layouted with conventional MOSFETs and therefore, the Wave layout style is an alternative layout to reduce the total die area of PPM.","PeriodicalId":318195,"journal":{"name":"2021 35th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130498784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Experimental Analysis of Trade-Off Between Transistor Efficiency and Unit Gain Frequency of Nanosheet NMOS Transistors 纳米片纳米mos晶体管效率与单位增益频率权衡的实验分析
2021 35th Symposium on Microelectronics Technology and Devices (SBMicro) Pub Date : 2021-08-23 DOI: 10.1109/SBMicro50945.2021.9585768
V. Silva, J. Martino, E. Simoen, A. Veloso, P. Agopian
{"title":"Experimental Analysis of Trade-Off Between Transistor Efficiency and Unit Gain Frequency of Nanosheet NMOS Transistors","authors":"V. Silva, J. Martino, E. Simoen, A. Veloso, P. Agopian","doi":"10.1109/SBMicro50945.2021.9585768","DOIUrl":"https://doi.org/10.1109/SBMicro50945.2021.9585768","url":null,"abstract":"This work presents a trade-off analysis between transistor efficiency (gm/ID which is proportional to the intrinsic voltage gain Av) and the unit gain frequency (fT) of the nanosheet (NSH) NMOS devices. The analyses were performed experimentally as a function of the inversion coefficient (weak, moderate, or strong inversion levels-IC) in order to determine the best operation region for optimization of both parameters. These analyses were performed with NSH NMOS for the channel length ranging from 28 nm to 200 nm. It was observed that the optimal operation point takes place in the transition between moderate and strong inversion (IC=10), where the highest value obtained for gm/ID x fT was found. In this optimum bias point the AV is 50 dB (L=200 nm) and 37 dB (L=28 nm) and fT is 7 GHz (L=200nm) and 160 GHz (L=28nm), which should be suitable for many applications.","PeriodicalId":318195,"journal":{"name":"2021 35th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"45 13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116069798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Junctionless Nanowire Transistors Based Common-Source Current Mirror 基于共源电流反射镜的无结纳米线晶体管
2021 35th Symposium on Microelectronics Technology and Devices (SBMicro) Pub Date : 2021-08-23 DOI: 10.1109/SBMicro50945.2021.9585731
André B. Shibutani, M. de Souza, R. Trevisoli, R. Doria
{"title":"Junctionless Nanowire Transistors Based Common-Source Current Mirror","authors":"André B. Shibutani, M. de Souza, R. Trevisoli, R. Doria","doi":"10.1109/SBMicro50945.2021.9585731","DOIUrl":"https://doi.org/10.1109/SBMicro50945.2021.9585731","url":null,"abstract":"In this article, a current mirror built with junctionless nanowire transistors (JNTs) is investigated for the first time. The study explores the influence of transistors’ width on the mirroring precision for input and output devices with different dimensions. The work has been performed through numerical simulations validated with experimental data and showed that the variation of devices’ width impacts the output characteristics differently from usually observed in current mirrors formed by inversion mode devices.","PeriodicalId":318195,"journal":{"name":"2021 35th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116808703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Improvement of Schottky Junctions for application in BESOI MOSFET 用于BESOI MOSFET的肖特基结改进
2021 35th Symposium on Microelectronics Technology and Devices (SBMicro) Pub Date : 2021-08-23 DOI: 10.1109/SBMicro50945.2021.9585745
Henrique A. Zangaro, R. Rangel, K. Sasaki, L. Yojo, J. Martino
{"title":"Improvement of Schottky Junctions for application in BESOI MOSFET","authors":"Henrique A. Zangaro, R. Rangel, K. Sasaki, L. Yojo, J. Martino","doi":"10.1109/SBMicro50945.2021.9585745","DOIUrl":"https://doi.org/10.1109/SBMicro50945.2021.9585745","url":null,"abstract":"In this work, an improvement of Schottky junction was performed for application in Back Enhanced BESOI MOSFET. It was observed that the formation of NiSi prior to the deposition of the aluminum on it, protects the Schottky junction from the aluminum interaction with Ni during thermal treatment. As a result, the Schottky junction obtained with this new process fabrication presents a better electrical behavior with ideality factor, n, close to 1 (n = 1.02 for Werner method and n = 0.95 for Gromov method) and Schottky barrier height, Φb = 0.42 eV.","PeriodicalId":318195,"journal":{"name":"2021 35th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114773371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Improved Back Enhanced SOI (BESOI) MOSFET by adding n-doped regions 通过添加n掺杂区改进背增强SOI (BESOI) MOSFET
2021 35th Symposium on Microelectronics Technology and Devices (SBMicro) Pub Date : 2021-08-23 DOI: 10.1109/SBMicro50945.2021.9585735
R. Sasaki, R. Rangel, D. A. Ramos, L. Yojo, J. Martino
{"title":"Improved Back Enhanced SOI (BESOI) MOSFET by adding n-doped regions","authors":"R. Sasaki, R. Rangel, D. A. Ramos, L. Yojo, J. Martino","doi":"10.1109/SBMicro50945.2021.9585735","DOIUrl":"https://doi.org/10.1109/SBMicro50945.2021.9585735","url":null,"abstract":"This paper reports the study of the Back Enhanced SOI (<sup>BE</sup>SOI) MOSFET improvement through the inclusion of ndoped regions on the drain and source regions underlapped with the gate. This study was performed using TCAD Synopsys Sentaurus simulator. The main characteristic of the original <sup>BE</sup>SOI MOSFET is the reconfigurable behavior, depending on the back-gate bias (V<inf>GB</inf>) the device can act as a p- or n-type transistor. However, the I<inf>on</inf> current is typically asymmetric. The proposed new structure by adding n-doped regions improves the drain current when the new <sup>BE</sup>SOI is in the n-type <sup>BE</sup>SOI configuration, which may take both transistor types to the same current level. The best results to L<inf>MP</inf> = 1 μm was obtained for V<inf>GB</inf> = |30| V, mainly when the transistor is in the triode region.","PeriodicalId":318195,"journal":{"name":"2021 35th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130163055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Electrical characterization of Si-based/SiO2/TiO2 heterostructures si基/SiO2/TiO2异质结构的电学表征
2021 35th Symposium on Microelectronics Technology and Devices (SBMicro) Pub Date : 2021-08-23 DOI: 10.1109/SBMicro50945.2021.9585756
M. L. D. da Silva, A. F. Oliveira, D. R. Huanca, W. Y. A. da Silva
{"title":"Electrical characterization of Si-based/SiO2/TiO2 heterostructures","authors":"M. L. D. da Silva, A. F. Oliveira, D. R. Huanca, W. Y. A. da Silva","doi":"10.1109/SBMicro50945.2021.9585756","DOIUrl":"https://doi.org/10.1109/SBMicro50945.2021.9585756","url":null,"abstract":"Two heterostructures based in the junction of titanium oxide, TiO2, and flat or porous silicon, PS, substrates were fabricated and their electrical properties were investigated through measuring the current-voltage and impedance electrochemical spectroscopy curves. The structural characterization reveals the successful deposition of TiO2 into the porous structure, which was also confirmed by the functional group analysis by the Fourier transform infrared spectroscopy. Concerning the electrical features, significant differences were found in charge transport behavior so that higher current intensity was recorded in the device based on porous silicon, despite its higher a.c resistance measured by impedance analysis. The fitting procedure of the current-voltage curves assuming the system is composed of three diodes points out that the possible cause for this behavior could be attributed to the role of the surface states in lowering the barrier potential. Such results are promising, as they allow the identification of the best methodology for the preparation of TiO2/silicon-based heterostructures that can be used in the photovoltaic and sensor field.","PeriodicalId":318195,"journal":{"name":"2021 35th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128831146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Temperature Influence on the Electrical Properties of Vertically Stacked Nanowire MOSFETs 温度对垂直堆叠纳米线mosfet电性能的影响
2021 35th Symposium on Microelectronics Technology and Devices (SBMicro) Pub Date : 2021-08-23 DOI: 10.1109/SBMicro50945.2021.9585748
J. C. Rodrigues, G. Mariniello, M. Cassé, S. Barraud, M. Vinet, O. Faynot, M. Pavanello
{"title":"Temperature Influence on the Electrical Properties of Vertically Stacked Nanowire MOSFETs","authors":"J. C. Rodrigues, G. Mariniello, M. Cassé, S. Barraud, M. Vinet, O. Faynot, M. Pavanello","doi":"10.1109/SBMicro50945.2021.9585748","DOIUrl":"https://doi.org/10.1109/SBMicro50945.2021.9585748","url":null,"abstract":"This paper aims at analyzing the electrical characteristics of 2-level Stacked Nanowire MOSFETs at low temperatures. Fundamental device parameters such as threshold voltage, subthreshold slope and transconductance are evaluated in the temperature range of 160K to 400K. The influence of fin width variation is also studied. An analytical model of multiple-gate nanowire MOSFETs is employed to explain the experimentally observed data. It is demonstrated that the threshold voltage increases linearly with the temperature reduction. Stacked nanowires with wider fin width presents larger threshold variation with temperature.","PeriodicalId":318195,"journal":{"name":"2021 35th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117173263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
e-mulate: a user-friendly software to calculate optoelectronic properties of quantum well systems E-mulate:一个计算量子阱系统光电特性的用户友好软件
2021 35th Symposium on Microelectronics Technology and Devices (SBMicro) Pub Date : 2021-08-23 DOI: 10.1109/SBMicro50945.2021.9585740
P. Pereira, G. Torelly, Matheus S. Lacerda, David R. Souza, J. E. Ruiz, Vinicius R. Souza, Luis A. Chipana, P. L. Souza, G. M. Penello, M. Pires
{"title":"e-mulate: a user-friendly software to calculate optoelectronic properties of quantum well systems","authors":"P. Pereira, G. Torelly, Matheus S. Lacerda, David R. Souza, J. E. Ruiz, Vinicius R. Souza, Luis A. Chipana, P. L. Souza, G. M. Penello, M. Pires","doi":"10.1109/SBMicro50945.2021.9585740","DOIUrl":"https://doi.org/10.1109/SBMicro50945.2021.9585740","url":null,"abstract":"We present e-mulate, an user-friendly software developed to calculate the electronic states of quantum well heterostructures. e-mulate was designed with a graphical user interface for users without previous coding skills. The unidimensional Schrödinger equation is numerically solved using transfer matrix and Numerov algorithms in the back-end. Essential figures of merit of optoelectronic devices, such as photodetectors are provided by the software: optical transition energies with their respective oscillator strengths, the absorption and the electronic transmission spectra. A comparison between the calculated absorption and experimental results of an In0.53Ga0.47As/In0.52Al0.48As quantum Bragg mirror photodetectors is presented as validation of the software.","PeriodicalId":318195,"journal":{"name":"2021 35th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131307083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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