温度对垂直堆叠纳米线mosfet电性能的影响

2021 35th Symposium on Microelectronics Technology and Devices (SBMicro) Pub Date : 2021-08-23 DOI:10.1109/SBMicro50945.2021.9585748

J. C. Rodrigues, G. Mariniello, M. Cassé, S. Barraud, M. Vinet, O. Faynot, M. Pavanello

{"title":"温度对垂直堆叠纳米线mosfet电性能的影响","authors":"J. C. Rodrigues, G. Mariniello, M. Cassé, S. Barraud, M. Vinet, O. Faynot, M. Pavanello","doi":"10.1109/SBMicro50945.2021.9585748","DOIUrl":null,"url":null,"abstract":"This paper aims at analyzing the electrical characteristics of 2-level Stacked Nanowire MOSFETs at low temperatures. Fundamental device parameters such as threshold voltage, subthreshold slope and transconductance are evaluated in the temperature range of 160K to 400K. The influence of fin width variation is also studied. An analytical model of multiple-gate nanowire MOSFETs is employed to explain the experimentally observed data. It is demonstrated that the threshold voltage increases linearly with the temperature reduction. Stacked nanowires with wider fin width presents larger threshold variation with temperature.","PeriodicalId":318195,"journal":{"name":"2021 35th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Temperature Influence on the Electrical Properties of Vertically Stacked Nanowire MOSFETs\",\"authors\":\"J. C. Rodrigues, G. Mariniello, M. Cassé, S. Barraud, M. Vinet, O. Faynot, M. Pavanello\",\"doi\":\"10.1109/SBMicro50945.2021.9585748\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper aims at analyzing the electrical characteristics of 2-level Stacked Nanowire MOSFETs at low temperatures. Fundamental device parameters such as threshold voltage, subthreshold slope and transconductance are evaluated in the temperature range of 160K to 400K. The influence of fin width variation is also studied. An analytical model of multiple-gate nanowire MOSFETs is employed to explain the experimentally observed data. It is demonstrated that the threshold voltage increases linearly with the temperature reduction. Stacked nanowires with wider fin width presents larger threshold variation with temperature.\",\"PeriodicalId\":318195,\"journal\":{\"name\":\"2021 35th Symposium on Microelectronics Technology and Devices (SBMicro)\",\"volume\":\"74 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-08-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 35th Symposium on Microelectronics Technology and Devices (SBMicro)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SBMicro50945.2021.9585748\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 35th Symposium on Microelectronics Technology and Devices (SBMicro)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SBMicro50945.2021.9585748","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

摘要

本文旨在分析2级堆叠纳米线mosfet在低温下的电学特性。在160K至400K的温度范围内评估了阈值电压、亚阈值斜率和跨导等基本器件参数。研究了翅片宽度变化的影响。采用多栅纳米线mosfet的解析模型来解释实验观测数据。结果表明，阈值电压随温度的降低呈线性增加。鳍宽越宽的堆叠纳米线随温度的阈值变化越大。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Temperature Influence on the Electrical Properties of Vertically Stacked Nanowire MOSFETs

This paper aims at analyzing the electrical characteristics of 2-level Stacked Nanowire MOSFETs at low temperatures. Fundamental device parameters such as threshold voltage, subthreshold slope and transconductance are evaluated in the temperature range of 160K to 400K. The influence of fin width variation is also studied. An analytical model of multiple-gate nanowire MOSFETs is employed to explain the experimentally observed data. It is demonstrated that the threshold voltage increases linearly with the temperature reduction. Stacked nanowires with wider fin width presents larger threshold variation with temperature.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2021 35th Symposium on Microelectronics Technology and Devices (SBMicro)

自引率

0.00%

发文量