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2007 14th International Conference on Mixed Design of Integrated Circuits and Systems最新文献

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An Undersampling Digital Microphone Utilising Second Order Noise Shaping 利用二阶噪声整形的欠采样数字传声器
2007 14th International Conference on Mixed Design of Integrated Circuits and Systems Pub Date : 2007-06-21 DOI: 10.1109/MIXDES.2007.4286155
S. Soell, B. Porr
{"title":"An Undersampling Digital Microphone Utilising Second Order Noise Shaping","authors":"S. Soell, B. Porr","doi":"10.1109/MIXDES.2007.4286155","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286155","url":null,"abstract":"Certain applications do not allow for feedback in delta-sigma converters due to circuit topologies and/or practical problems inherent to feedback loops. As a result, this paper presents the analysis and implementation of a digital microphone utilizing a feed-forward only sigma delta A/D converter comprising of a Schmitt trigger, capacitor and sampling D-FF to digitize data. The system is analyzed mathematically and performance results are given. To further improve upon the obtained results, the topology is extended to cascaded structure utilizing an all digital second modulator to obtain second-order noise shaping. This is a marked departure from prior art and results in significant improvements in the performance over a first-order topology.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"35 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116643494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Novel Step-Ramp Signal for Testing ADCS and DACS 用于ADCS和DACS测试的新型阶梯-斜坡信号
2007 14th International Conference on Mixed Design of Integrated Circuits and Systems Pub Date : 2007-06-21 DOI: 10.1109/MIXDES.2007.4286217
Y. Wen
{"title":"Novel Step-Ramp Signal for Testing ADCS and DACS","authors":"Y. Wen","doi":"10.1109/MIXDES.2007.4286217","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286217","url":null,"abstract":"This paper presents a novel step-ramp signal (SRS) for testing analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). A regulated clock signal (RCS) comes from regulating the frequency, duty cycle and amplitude of the system clock pulse which also serves as a trig pulse of a reference counter. The RCS is integrated by an Integrator to transform into the SRS which can accurately correspond with the output codes of the reference counter. With gradually increasing duty cycles according to the voltages of the SRS, the larger duty cycle the longer integration time is set up. Larger voltages from the integration of prolonged duty cycles are generated to compensate linkage currents at the capacitor. The problem of higher voltages resulting higher leakage currents at the capacitor in the Integrator can be overcome. The simulation results show that the accuracies of all ramp pieces of the SRS are within plusmn1/2LSB. The main advantages of the SRS for testing converters include accurate correspondence between the SRS and the reference counter and digital designs in linkage current compensation and in test response analyzers.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122125463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
The Electrothermal Analysis of a Switched Mode Voltage Regulator 开关模式稳压器的电热分析
2007 14th International Conference on Mixed Design of Integrated Circuits and Systems Pub Date : 2007-06-21 DOI: 10.1109/MIXDES.2007.4286232
K. Górecki, J. Zarebski
{"title":"The Electrothermal Analysis of a Switched Mode Voltage Regulator","authors":"K. Górecki, J. Zarebski","doi":"10.1109/MIXDES.2007.4286232","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286232","url":null,"abstract":"The paper concerns the electrothermal analysis of the switched mode voltage regulator. It presented the calculations results of the characteristics in the steady state of the regulator containing the UC3842 controller and the boost converter. The correctness of the obtained calculations results was verified experimentally.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124854779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
FPGA Based Accelerator for Simulated Annealing with Greedy Perturbations 基于FPGA的贪婪扰动模拟退火加速器
2007 14th International Conference on Mixed Design of Integrated Circuits and Systems Pub Date : 2007-06-21 DOI: 10.1109/MIXDES.2007.4286166
M. Lukowiak, B. Cody
{"title":"FPGA Based Accelerator for Simulated Annealing with Greedy Perturbations","authors":"M. Lukowiak, B. Cody","doi":"10.1109/MIXDES.2007.4286166","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286166","url":null,"abstract":"This paper discusses design of an field programmable gate array (FPGA) based hardware accelerator for a standard cell placement tool. A software program was used to determine the bottlenecks in the simulated annealing (SA) algorithm with greedy perturbations and dynamic cooling schedule. A solution implementing computing platform with specialized hardware configurations inside an FPGA was investigated as having the possibility to improve the efficiency of the SA-based algorithms.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125319239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Correction to Thermal Impedance Measurements Made Under Non-Equilibrium Conditions 非平衡条件下热阻抗测量的修正
2007 14th International Conference on Mixed Design of Integrated Circuits and Systems Pub Date : 2007-06-21 DOI: 10.1109/MIXDES.2007.4286186
F. Masana
{"title":"Correction to Thermal Impedance Measurements Made Under Non-Equilibrium Conditions","authors":"F. Masana","doi":"10.1109/MIXDES.2007.4286186","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286186","url":null,"abstract":"The measurement of semiconductor device thermal impedance is in general easier to perform experimentally if the heating and measuring phases are performed separately in order to avoid mutual interference. However, unless we are able to guarantee that the system is in equilibrium before performing the measurement, the result is not the real thermal impedance. This work presents a method to extend the validity of a measurement made under non-equilibrium conditions to fit the real value of thermal impedance.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125656213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Parameter Extraction for Simplified RF NMOSFET Equivalent Circuit using Spice 基于Spice的简化射频NMOSFET等效电路参数提取
2007 14th International Conference on Mixed Design of Integrated Circuits and Systems Pub Date : 2007-06-21 DOI: 10.1109/MIXDES.2007.4286205
G. Angelov, M. Hristov, O. Antonova, E. Gadjeva
{"title":"Parameter Extraction for Simplified RF NMOSFET Equivalent Circuit using Spice","authors":"G. Angelov, M. Hristov, O. Antonova, E. Gadjeva","doi":"10.1109/MIXDES.2007.4286205","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286205","url":null,"abstract":"In the paper, a parameter extraction approach is proposed to a simplified small-signal NMOSFET equivalent circuit utilizing Cadence PSpice circuit simulator. A direct extraction procedure is realized based on the two-port Y-parameters. The computer realization of the developed extraction procedure is performed using parameterization of the model. Based on postprocessing in the graphical analyzer Probe utilizing corresponding macrodefinitions, the two-port Y-parameters are calculated. Verification of the extraction methodology is made by comparing the simulated and experimental results for the Y-parameters.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130387483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Facet Heating Mechanisms in High Power Semiconductor Lasers Investigated by Spatially Resolved Thermoreflectance 利用空间分辨热反射研究高功率半导体激光器的小面加热机制
2007 14th International Conference on Mixed Design of Integrated Circuits and Systems Pub Date : 2007-06-21 DOI: 10.1109/MIXDES.2007.4286215
D. Pierścińska, K. Pierściński, A. Kozłowska, A. Malag, A. Jasik, M. Bugajski
{"title":"Facet Heating Mechanisms in High Power Semiconductor Lasers Investigated by Spatially Resolved Thermoreflectance","authors":"D. Pierścińska, K. Pierściński, A. Kozłowska, A. Malag, A. Jasik, M. Bugajski","doi":"10.1109/MIXDES.2007.4286215","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286215","url":null,"abstract":"Thermal properties, degradation behaviour and optical and current contributions to facet heating of high power diode lasers emitting at 808 nm are analysed. The investigated devices with non-injected facets are designed to reduce carrier recombination at the facet surface. Spatially resolved thermoreflectance spectroscopy is used to measure temperature distribution maps over the laser facet. This study compares the facet temperature distributions for fresh (undamaged) and degraded laser. The measurements results indicate for the strong contribution of reabsorption of the laser emission to the overall facet heating for lasers with non-injected facets.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129130645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Speed Enhancement and Linearity Analysis for a Rail-to-Rail Input Opamp in 120nm CMOS 120nm CMOS轨对轨输入运放的速度提升与线性分析
2007 14th International Conference on Mixed Design of Integrated Circuits and Systems Pub Date : 2007-06-21 DOI: 10.1109/MIXDES.2007.4286181
W. Yan, Horst Zimmermann
{"title":"Speed Enhancement and Linearity Analysis for a Rail-to-Rail Input Opamp in 120nm CMOS","authors":"W. Yan, Horst Zimmermann","doi":"10.1109/MIXDES.2007.4286181","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286181","url":null,"abstract":"This paper introduces a fully differential opamp with constant large-and small-signal behavior rail-to-rail input stage. A compensation strategy is presented to extend the bandwidth. The linearity issue of the compensation is discussed. A test chip is implemented in a standard 120 nm CMOS process, with the measured signal variation of about 4.43% as well as a GBW of 135 MHz. Experimental results verify the performance.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"235 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126630387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Device Level Electrothermal Analysis of Integrated Resistors 集成电阻的器件级电热分析
2007 14th International Conference on Mixed Design of Integrated Circuits and Systems Pub Date : 2007-06-21 DOI: 10.1109/MIXDES.2007.4286187
B. Vermeersch, G. De Mey
{"title":"Device Level Electrothermal Analysis of Integrated Resistors","authors":"B. Vermeersch, G. De Mey","doi":"10.1109/MIXDES.2007.4286187","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286187","url":null,"abstract":"This paper presents the electrothermal simulation of integrated thin film resistors. Both the thermal and electrical problem is tackled by a semi-analytical method, without the need of generating an equivalent distributed network. As the electrical conductivity is temperature dependent, self-heating of the resistor will alterate the current distribution, leading to a non-uniform power dissipation. This then provokes a change of the temperature distribution, explaining the electrothermal coupling. Examples are given for various practical resistor designs. After a few iterations stable values for the electrical and thermal resistance and temperature and power distributions are obtained. The results show that even if one would anticipate the self-heating process based on an estimated average temperature, the behaviour will still deviate from the original design. This is caused entirely by the non-uniformity of the distributions inside the component.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114837658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Hardware-Software Codesign of a Fingerprint Alignment Processor 指纹定位处理器的软硬件协同设计
2007 14th International Conference on Mixed Design of Integrated Circuits and Systems Pub Date : 2007-06-21 DOI: 10.1109/MIXDES.2007.4286246
M. Fons, F. Fons, E. Cantó
{"title":"Hardware-Software Codesign of a Fingerprint Alignment Processor","authors":"M. Fons, F. Fons, E. Cantó","doi":"10.1109/MIXDES.2007.4286246","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286246","url":null,"abstract":"Within the biometrics field, the development of an automatic personal authentication system is nowadays an open research problem. Most of the difficulties rely on the complexity and the computational power needed to implement an algorithm reliable enough to guarantee the validity of the recognition system even when only low-quality biometric information is available from the users. Apart from the inherent complexity of the biometric algorithm, there exist many additional requirements for the application: high-security level, real-time characteristics and low-cost. All these factors originate a technical challenge. A compromise between the final application performance and the amount of resources needed to implement the system exists. Following this direction, the design of a fingerprint alignment processor developed by means of hardware-software codesign techniques is presented in this paper. The performance achieved with this processor is compared against the performance reached with an only software-oriented solution. The acceleration factor achieved by the hardware proves the feasibility of real-time applications, which is not guaranteed when developing the same algorithm under purely-software platforms.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124436743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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