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Tradeoffs and Optimization in Analog CMOS Design 模拟CMOS设计中的权衡与优化
2007 14th International Conference on Mixed Design of Integrated Circuits and Systems Pub Date : 2008-08-04 DOI: 10.1109/mixdes.2007.4286119
D. Binkley
{"title":"Tradeoffs and Optimization in Analog CMOS Design","authors":"D. Binkley","doi":"10.1109/mixdes.2007.4286119","DOIUrl":"https://doi.org/10.1109/mixdes.2007.4286119","url":null,"abstract":"The selection of drain current, inversion coefficient, and channel length for each MOS device in an analog circuit results in significant tradeoffs in performance. The selection of inversion coefficient, which is a numerical measure of MOS inversion, enables design freely in weak, moderate, and strong inversion and facilitates optimum design. Here, channel width required for layout is easily found and implicitly considered in performance expressions. This paper gives hand expressions motivated by the EKV MOS model and measured data for MOS device performance, inclusive of velocity saturation and other small-geometry effects. A simple spreadsheet tool is then used to predict MOS device performance and map this into complete circuit performance. Tradeoffs and optimization of performance are illustrated by the design of three, 0.18-mum CMOS operational transconductance amplifiers optimized for DC, balanced, and AC performance. Measured performance shows significant tradeoffs in voltage gain, output resistance, transconductance bandwidth, input-referred flicker noise and offset voltage, and layout area.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124071126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 290
Integrated Thermo-Electro-Mechanical Modeling of 3D e-Cubes Structures 三维电子立方体结构的热-电-机械集成建模
2007 14th International Conference on Mixed Design of Integrated Circuits and Systems Pub Date : 2007-06-21 DOI: 10.1109/MIXDES.2007.4286171
G. Janczyk, T. Bieniek, P. Janus, A. Kociubiński, P. Grabiec, J. Szynka, M.S. Reitz, P. Schneider, E. Kaulfersch, J. Weber
{"title":"Integrated Thermo-Electro-Mechanical Modeling of 3D e-Cubes Structures","authors":"G. Janczyk, T. Bieniek, P. Janus, A. Kociubiński, P. Grabiec, J. Szynka, M.S. Reitz, P. Schneider, E. Kaulfersch, J. Weber","doi":"10.1109/MIXDES.2007.4286171","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286171","url":null,"abstract":"The complex silicon systems formed by the several specialized devices like SOC, RF devices, power devices, MEMS wafers are fabricated in dedicated technologies. If the designer attempts to integrate them into the one big multifunctional system, he meets the new, yet unexplored fields for the multidisciplinary, mutually dependent thermal, electrical, EM and mechanical parameters modeling. This article attempts to clarify, and presents how to simplify this problem.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"12 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116771295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Parameters Identification of Embedded PTAT Temperature Sensors for CMOS Circuits CMOS电路中嵌入式PTAT温度传感器的参数辨识
2007 14th International Conference on Mixed Design of Integrated Circuits and Systems Pub Date : 2007-06-21 DOI: 10.1109/MIXDES.2007.4286190
A. Golda, A. Kos
{"title":"Parameters Identification of Embedded PTAT Temperature Sensors for CMOS Circuits","authors":"A. Golda, A. Kos","doi":"10.1109/MIXDES.2007.4286190","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286190","url":null,"abstract":"In this paper, we describe the parameters identification results of PTAT (proportional to absolute temperature) temperature sensors that are implemented in the test chip and dedicated to CMOS integrated circuits. Theirs principles of operation are based on the vertical PNP structure. These sensing elements are uniformly distributed on the chip surface. The chip is dedicated to analyses and verifications of various electro-thermal phenomena in microelectronic VLSI circuits and is fabricated in CMOS 0.7 mum technology. The measurements were performed in a thermal chamber for the temperature range of 288-358 K. The achieved sensitivities of the temperature sensors are within following limits 3.44 to 4.82 mV/K.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124806521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Analog, Continuous Time, Fully Parallel, Programmable Image Processor Based on Vector Gilbert Multiplier 模拟，连续时间，全并行，基于矢量吉尔伯特乘法器的可编程图像处理器
2007 14th International Conference on Mixed Design of Integrated Circuits and Systems Pub Date : 2007-06-21 DOI: 10.1109/MIXDES.2007.4286156
R. Dlugosz
{"title":"Analog, Continuous Time, Fully Parallel, Programmable Image Processor Based on Vector Gilbert Multiplier","authors":"R. Dlugosz","doi":"10.1109/MIXDES.2007.4286156","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286156","url":null,"abstract":"A conception as well as a CMOS implementation of the analog, ultra low power and fully parallel image processor have been presented in this paper. Proposed circuit bases on the 2-D FIR filters realized using the Gilbert vector multiplier. Proposed filter enables realization of various lowpass and highpass 2-D FIR filter masks. Both the mask dimensions and values of the filter coefficients can be programmed using several dozen digital signals and several DC currents. Proposed image processor does not use the clock generator, what simplifies the overall circuit's structure and reduces the noise level. An example (6times6) image processor that enables filtering with a 3times3 mask has been implemented in CMOS 0.18 mum process. This circuit calculates 36 pixels in parallel every 1 mus, dissipating power about 20 muW. The image resolution can be easily enlarged by a parallel connection of many designed 6times6 cells.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122705799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Investigation of Substrate Noise Coupling and Isolation Characteristics for a 0.35UM HV CMOS Technology 0.35UM高压CMOS技术衬底噪声耦合与隔离特性研究
2007 14th International Conference on Mixed Design of Integrated Circuits and Systems Pub Date : 2007-06-21 DOI: 10.1109/MIXDES.2007.4286198
W. Pflanzl, E. Seebacher
{"title":"Investigation of Substrate Noise Coupling and Isolation Characteristics for a 0.35UM HV CMOS Technology","authors":"W. Pflanzl, E. Seebacher","doi":"10.1109/MIXDES.2007.4286198","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286198","url":null,"abstract":"This paper presents the characterization of substrate noise coupling and the isolation capability of ohmic substrate contacts in a HV CMOS technology. Layout variations of contact sizes, distances, and several p+ guard structures are subject of this research. Metal shielded DUT fixtures have been developed to improve the reliability and accuracy of the measurements. All test cases are fabricated with a 0.35 mum HV CMOS technology (Vmax <= 120 V). This process features high resistive native substrate (20 Ohm.cm) together with a 0.5 Ohm.cm pwell. The modeling section describes the distributed substrate \"resistor\" and the DUT fixture behavior.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114483270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Implementation of Cholesky LLT-Decomposition Algorithm in FPGA-Based Rational Fraction Parallel Processor 基于fpga的有理分式并行处理器中Cholesky llt分解算法的实现
2007 14th International Conference on Mixed Design of Integrated Circuits and Systems Pub Date : 2007-06-21 DOI: 10.1109/MIXDES.2007.4286169
O. Maslennikow, P. Ratuszniak, A. Sergyienko
{"title":"Implementation of Cholesky LLT-Decomposition Algorithm in FPGA-Based Rational Fraction Parallel Processor","authors":"O. Maslennikow, P. Ratuszniak, A. Sergyienko","doi":"10.1109/MIXDES.2007.4286169","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286169","url":null,"abstract":"In this paper, the fixed size processor array architecture, which is destined for realization of LLT-decomposition of symmetrical positively definite matrices based on Cholesky algorithm, is proposed. In order to implementation of this architecture in modern FPGA devices, the arithmetic unit (AU) operating in the rational fraction arithmetic is designed. This AU is adapted to realization in the Xilinx reconfigurable platforms Virtex II or Virtex 4 families and its hardware complexity is up to 4,5 times less in comparison with similar AUs operating with float-point numbers.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128215616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Behavioural Modelling and Simulation of Dual Cascaded PLL Based Frequency Synthesizer 基于双级联锁相环频率合成器的行为建模与仿真
2007 14th International Conference on Mixed Design of Integrated Circuits and Systems Pub Date : 2007-06-21 DOI: 10.1109/MIXDES.2007.4286194
A. Telba, S.M. Qasim, J. Noras, B. Almashary, M. A. El Ela
{"title":"Behavioural Modelling and Simulation of Dual Cascaded PLL Based Frequency Synthesizer","authors":"A. Telba, S.M. Qasim, J. Noras, B. Almashary, M. A. El Ela","doi":"10.1109/MIXDES.2007.4286194","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286194","url":null,"abstract":"In this paper, behavioural model of a dual cascaded phase locked loop (PLL) based frequency synthesizer is presented and the results are validated through SystemVision simulation using very high speed Integrated circuit hardware description language-analog mixed signal (VHDL-AMS). Dual cascaded PLL consists of a low jitter PLL employing a voltage controlled crystal oscillator (VCXO) followed by a wideband PLL employing normal voltage controlled oscillator (VCO). The advantage of using dual PLL in cascade configuration is that it provides very good performance in terms of low jitter as compared to a single PLL based frequency synthesizer. Simulation results obtained are in good agreement with the theoretical calculations.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128505297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Integral Interface - Universal Communication Interface for FPGA-Based Projects 集成接口-基于fpga项目的通用通信接口
2007 14th International Conference on Mixed Design of Integrated Circuits and Systems Pub Date : 2007-06-21 DOI: 10.1109/MIXDES.2007.4286131
A. Piotrowski, S. Tarnowski, G. Jablonski, A. Napieralski
{"title":"Integral Interface - Universal Communication Interface for FPGA-Based Projects","authors":"A. Piotrowski, S. Tarnowski, G. Jablonski, A. Napieralski","doi":"10.1109/MIXDES.2007.4286131","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286131","url":null,"abstract":"During the development process it is very important to assure reliable communication between individual parts of the system. In a special case, when the system is implemented in the FPGA chip, possible solution of communication problem encompass not only ready-made solutions but also especially designed interfaces adapted to specific projects. This paper highlights Integral Interface -universal communication interface for applications in FPGA chip. In addition, presented paper describes specialized program that automatically generates VHDL source code for an interface and supplementary components.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128616760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Evolution of the Classical Functional Integration Towards a 3D Heterogeneous Functional Integration 经典功能集成向三维异构功能集成的演变
2007 14th International Conference on Mixed Design of Integrated Circuits and Systems Pub Date : 2007-06-21 DOI: 10.1109/MIXDES.2007.4286116
J. Sanchez, A. Bourennane, M. Breil, P. Austin, M. Brunet, J. Laur
{"title":"Evolution of the Classical Functional Integration Towards a 3D Heterogeneous Functional Integration","authors":"J. Sanchez, A. Bourennane, M. Breil, P. Austin, M. Brunet, J. Laur","doi":"10.1109/MIXDES.2007.4286116","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286116","url":null,"abstract":"This paper presents a brief overview of the monolithic integration in the field of power electronics. Emphasis is mainly put on the functional integration concept. The role that this mode of integration, according to its classical definition, played to enable the monolithic integration of the power device with auxiliary elements (mainly protections and supply) for the realization of new functions dedicated for medium power applications is highlighted. At that end, some of the recent realizations are described in order to showcase some of the potentialities of this mode of integration. Furthermore, to extend further the classical integration towards a 3D \"heterogeneous\" functional integration, an example that highlights the improvements that should be achieved at the device's level as well as at the device's environment level, for the development of new power integrated functions for AC applications, is discussed. The last part deals with the technology process evolution for the realization of the active devices as well as the passive elements. In this part, a flexible technological process and its importance in the development of more complex functions, implemented in 3D within the silicon die volume and at the surface, is described in more detail.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"316 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124294688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Experiments and Modeling of Dynamic Floating Body Effects in 1T-Dram Fully Depleted SOI Devices 1T-Dram全耗尽SOI器件中动态浮体效应的实验与建模
2007 14th International Conference on Mixed Design of Integrated Circuits and Systems Pub Date : 2007-06-21 DOI: 10.1109/MIXDES.2007.4286125
M. Bawedin, S. Cristoloveanu, V. Dessard, Denis Flandre
{"title":"Experiments and Modeling of Dynamic Floating Body Effects in 1T-Dram Fully Depleted SOI Devices","authors":"M. Bawedin, S. Cristoloveanu, V. Dessard, Denis Flandre","doi":"10.1109/MIXDES.2007.4286125","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286125","url":null,"abstract":"We describe the transient floating-body mechanism which occurs in fully depleted SOI transistors and leads to a memory effect. A physics-based model for the potential variation with time is proposed and validated by numerical simulations. This model reproduces and clarifies the operation of the novel capacitor-less MSDRAM, the properties of which are discussed.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126490297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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