0.35UM高压CMOS技术衬底噪声耦合与隔离特性研究

2007 14th International Conference on Mixed Design of Integrated Circuits and Systems Pub Date : 2007-06-21 DOI:10.1109/MIXDES.2007.4286198

W. Pflanzl, E. Seebacher

{"title":"0.35UM高压CMOS技术衬底噪声耦合与隔离特性研究","authors":"W. Pflanzl, E. Seebacher","doi":"10.1109/MIXDES.2007.4286198","DOIUrl":null,"url":null,"abstract":"This paper presents the characterization of substrate noise coupling and the isolation capability of ohmic substrate contacts in a HV CMOS technology. Layout variations of contact sizes, distances, and several p+ guard structures are subject of this research. Metal shielded DUT fixtures have been developed to improve the reliability and accuracy of the measurements. All test cases are fabricated with a 0.35 mum HV CMOS technology (Vmax <= 120 V). This process features high resistive native substrate (20 Ohm.cm) together with a 0.5 Ohm.cm pwell. The modeling section describes the distributed substrate \"resistor\" and the DUT fixture behavior.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Investigation of Substrate Noise Coupling and Isolation Characteristics for a 0.35UM HV CMOS Technology\",\"authors\":\"W. Pflanzl, E. Seebacher\",\"doi\":\"10.1109/MIXDES.2007.4286198\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the characterization of substrate noise coupling and the isolation capability of ohmic substrate contacts in a HV CMOS technology. Layout variations of contact sizes, distances, and several p+ guard structures are subject of this research. Metal shielded DUT fixtures have been developed to improve the reliability and accuracy of the measurements. All test cases are fabricated with a 0.35 mum HV CMOS technology (Vmax <= 120 V). This process features high resistive native substrate (20 Ohm.cm) together with a 0.5 Ohm.cm pwell. The modeling section describes the distributed substrate \\\"resistor\\\" and the DUT fixture behavior.\",\"PeriodicalId\":310187,\"journal\":{\"name\":\"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems\",\"volume\":\"19 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-06-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MIXDES.2007.4286198\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MIXDES.2007.4286198","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

本文介绍了高压CMOS技术中基片噪声耦合的特性和基片欧姆触点的隔离能力。布局变化的接触尺寸，距离，和几个p+保护结构是本研究的主题。为了提高测量的可靠性和准确性，开发了金属屏蔽的被测夹具。所有测试用例均采用0.35 μ m HV CMOS技术(Vmax <= 120 V)制造。该工艺具有高电阻原生衬底(20欧姆.cm)和0.5欧姆的电阻。cm pwell。建模部分描述了分布式基板“电阻”和被测装置的行为。

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Investigation of Substrate Noise Coupling and Isolation Characteristics for a 0.35UM HV CMOS Technology

This paper presents the characterization of substrate noise coupling and the isolation capability of ohmic substrate contacts in a HV CMOS technology. Layout variations of contact sizes, distances, and several p+ guard structures are subject of this research. Metal shielded DUT fixtures have been developed to improve the reliability and accuracy of the measurements. All test cases are fabricated with a 0.35 mum HV CMOS technology (Vmax <= 120 V). This process features high resistive native substrate (20 Ohm.cm) together with a 0.5 Ohm.cm pwell. The modeling section describes the distributed substrate "resistor" and the DUT fixture behavior.

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2007 14th International Conference on Mixed Design of Integrated Circuits and Systems

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