Speed Enhancement and Linearity Analysis for a Rail-to-Rail Input Opamp in 120nm CMOS

Abstract

This paper introduces a fully differential opamp with constant large-and small-signal behavior rail-to-rail input stage. A compensation strategy is presented to extend the bandwidth. The linearity issue of the compensation is discussed. A test chip is implemented in a standard 120 nm CMOS process, with the measured signal variation of about 4.43% as well as a GBW of 135 MHz. Experimental results verify the performance.