1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers最新文献_第4页

An NMOS pipelined image processor using quaternary logic 采用四元逻辑的NMOS流水线图像处理器

1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156822

M. Kameyama, T. Hanyu, M. Esashi, T. Higuchi

引用次数: 3

The effect of scaling upto future analog/digital systems 扩展到未来模拟/数字系统的影响

1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156850

J. McCreary

引用次数: 0

An 85ns 1Mb DRAM in a plastic DIP 一个85ns 1Mb的塑料DIP内存

1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156852

Y. Inoue, T. Murotani, Y. Fukuzoh, K. Hayano, T. Fujii, K. Minami, K. Nakamura, M. Kikuchi

引用次数: 14

Custom and semi-custom design approaches for the future 面向未来的定制和半定制设计方法

1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156845

A. Feller, C. Gwyn

引用次数: 0

Fault tolerant techniques for memory components 内存组件的容错技术

1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156843

M. Kubo, S. Chou

引用次数: 6

An IEEE802.5 compatible LAN controller with on-chip ROM 一个与片上ROM兼容的IEEE802.5局域网控制器

1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156801

A. Szczepanek, B. Shore, S. Hubbins, C. Hull, A. Smith, H. Watters, M. McGregor, R. Meads

引用次数: 2

Page mode programming 1Mb CMOS EPROM 页面模式编程1Mb CMOS EPROM

1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156766

Thpm, Takaaki Hagiwara, Hitoshi Matsuo, Minoru Fukuda, Yoh-ichi Matsuno, T. Furuno, Ken-ichi Kuroda, Tokumasa Yasui, Hisao Katto

{"title":"Page mode programming 1Mb CMOS EPROM","authors":"Thpm, Takaaki Hagiwara, Hitoshi Matsuo, Minoru Fukuda, Yoh-ichi Matsuno, T. Furuno, Ken-ichi Kuroda, Tokumasa Yasui, Hisao Katto","doi":"10.1109/ISSCC.1985.1156766","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156766","url":null,"abstract":"THIS PAPER WILL DESCRIBE a 1Mb CMOS EPROM with fast page mode programming. The EPROM was fabricated using: (I)-high voltage MOS structure with Lightly Doped Drain (LDD), (Z)-double poly N-well CMOS, and (3)-1p minimum gate length for memory transistors. This technology afforded a reduction of cell size to 19.27p2. Thus, it was possible to obtain 1Mb integration in a chip that is 6.0 x 6.56mm2. Scaling down of the memory transistor to a 1p gate length resulted in a wide threshold voltage shift with programming of 11-13V and 0.5ms. Organized as 128K x 8b, the EPROM has both page-mode and conventional byte-mode operation. In page-mode programming, the EPROM accepts four bytes of input data sequentically and programs them at a time; Figure 1. The mode enables programming with time comparable to 256K EPROM’. In this mode, four bytes of input data are stored in 32 latches, and gates of switching transistors on high voltage paths to memory bit lines are controlled by latch outputs when the program enable signal is applied; Figure 2. In a conventional programming mode, the latches are bypassed and the input data controls the switching transistors. A CMOS current sense amplifier with a feedback loop is used; Figure 3. The bit line voltage is lowered (about 1V) to prevent soft writing during read operation. The amplifier has a wide margin for reading operation with a maximum supply voltage of more than TV. Figure 4 shows a microphotograph of the chip. Read access waveforms arc in Figure 5 . Typical access time is 140ns. Power supply current is typically 5mA in active mode and less than IpA in standby mode.","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116972537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

A word-wide 1Mb ROM with error correction 具有纠错功能的世界范围1Mb ROM

1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156821

H. Davis

引用次数: 1

A/D architectures of the future 未来的A/D架构

1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156846

R. Brodersen, J. Rabaey

引用次数: 0

A programmable 80ns 1Mb CMOS EPROM 可编程80ns 1Mb CMOS EPROM

1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156767

S. Saito, S. Tanaka, S. Atsumi, K. Yoshikawa, M. Sato, K. Makita, S. Mori, H. Nozawa, T. Iizuka

引用次数: 9