1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers最新文献_第5页

A 16-levels/cell dynamic memory 16级/单元动态存储器

1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156858

M. Aoki, Y. Nakagome, M. Horiguchi, S. Ikenaga, K. Shimohigashi

引用次数: 35

Computing for artificial intelligence 人工智能计算

1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156741

D. Secombe

引用次数: 0

Super chips for artificial intelligence 人工智能的超级芯片

1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156723

R. Reddy

{"title":"Super chips for artificial intelligence","authors":"R. Reddy","doi":"10.1109/ISSCC.1985.1156723","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156723","url":null,"abstract":"There is at least one field - artificial intelligence - that can effectively utilize air of the projected advances of semiconductor technology for the foreseeable future. The potential applications will be just as widespread, with education, health, industry, and service sectors among the many areas leading to a large demand for highly sophisticated solid state components. This address will assess these expanding virtues and their effect on the IC. Currently prevailing views about the future demand for high-powered computational elements are sometimes misguided. One such myth says that the demand for 32b (or larger) processors is likely to be limited because most applications do not need so much computational power. What these estimates fail to take into account are the computational needs of error-tolerance and user-friendliness that are essential if we expect ordinary mortals to use tomorrow's microcomputers effectively. The second myth stems from the view that a high powered LISP computer will be adequate to handle all of AI's computing needs. There are many topics that arise in AI for which the LISP machines alone are not adequate: perception problems for vision and speech, motor problems of manipulation and mobility in robotics, symbol manipulation problems of language, repetitive knowledge, recognition of rule-based inference in expert systems, combinatorial search in game playing and puzzle solving, massively parallel processing for instantaneous extraction and matching of relevant information from large knowledge bases. Each of these problems involves a wide variety of computational tasks, making it difficult to select any one architecture as the most desirable. A more probable AI architecture would be a multiprocessor structure with a large number of asymmetric processing elements sharing a large knowledge base. Furthermore, the trend from VLSI to ULSI will be towards higher degrees of Integration leading to higher functionality. A million-element chip might include functions currently requiring four or five chips. CPU, virtual memory, floating point arithmetic, array processor and cache. A hundred-million element chip might contain a 100 processor system with a common bus to a larger external shared memory. It is important to note that all of the hundred processors need not be identical. Processing elements should have dynamically alterable PLAs, leading to tailored architectures for different computational tasks. A billion-element super-chip might provide a 100 megabyte common memory and 100 processing elements on a single chip, along with A/D and D/A and networking interfaces. Even a super chip could barely perform many of these AI problems. A review of the foregoing problems illustrates the need for flexible and powerful computational elements in the future. It is indeed possible that we can haven billion element super chip by the turn of the century: it is interesting to speculate how we might use it!","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131397068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

A 1Mb DRAM with a folded capacitor cell structure 具有折叠电容单元结构的1Mb DRAM

1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156855

F. Horiguchi, Y. Itoh, H. Iizuka, M. Ogura, F. Masuoka

引用次数: 7

A 500MHz 8b DAC 一个500MHz 8b DAC

1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156809

K. Maio, S. Hayashi, M. Hotta, N. Yokozawa, T. Watanabe, S. Ueda

引用次数: 6

An 8MHz 8b CMOS subranging ADC 8MHz 8b CMOS分位ADC

1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156806

A. Dingwall, V. Zazzu

引用次数: 15

A 2.56Mb/s digital local-loop transmitter/receiver 2.56Mb/s的数字本地环路发射机/接收机

1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156793

D. Yarak, J. Hogeboom, A. Anderson, D. Harrison

引用次数: 2

A 15ns 64K bipolar SRAM 15ns 64K双极SRAM

1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156835

R. Heald, W. Herndon, In-Nan Wu, Si-Yu Chen

{"title":"A 15ns 64K bipolar SRAM","authors":"R. Heald, W. Herndon, In-Nan Wu, Si-Yu Chen","doi":"10.1109/ISSCC.1985.1156835","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156835","url":null,"abstract":"THIS PAPER WILL DESCRIBE a 64K bipolar SRAM with a cell size of 1 9 0 ~ 2 and 2p features that resulted in an overall die size of 38,608 square mils. Silicided polysilicon has been used to interconnect crosscoupled transistors, polysilicon resistors as load devices, and lateral polysilicon diodes for bit-line coupling devices. Of the six components required for the standard symmetrical static RAM, four are polysilicon. The cross-coupled transistors are collector-up transistors on a buried layer shared by 8 cells. The cell circuit is shown in Figure 1 and the cell layout in Figure 2. Cell operation is outlined in Table 1. Performance of most large memories is limited by the time required to charge and discharge large capacitors associated with word or bit lines. In this cell the longest time delay is in the charging and discharging of the buried layer-substrate capacitor on the selected word line. This delay has been minimized by using divided word lines or squad addressed architecture. The use of squads comprised of 8 cells each results in a 25% increase in array area, but reduces the effective word line capacitance to as little as 2% of its value without squads. The organization of a squad with 8 cells, a resistor and a transistor is shown in Figure 3. The squad driver transistor sinks the high current from the selected squad. The squad resistor recovers the squad to the standby level and sinks the standby current from the squad. The use of silicided polysilicon as the local interconnect within the cell permits three layers of interconnect and allows the use of the divided word line architecture without an area penalty.","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"220 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116227108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

An 8b microcomputer for implantable biomedical applications 用于植入式生物医学应用的8b微型计算机

1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156749

L. Stotts, R. Baker, J. Miner

引用次数: 4

A single chip signal processor for CCITT standard ADPCM codec 单片信号处理器，用于CCITT标准ADPCM编解码器

1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156840

M. Sato, Y. Ishikawa, T. Nishitani, T. Kato, H. Saita, Y. Aoki

引用次数: 5