1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers最新文献

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High speed LSI technologies challenging the CMOS VLSI era 高速LSI技术挑战CMOS VLSI时代
1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156842
P. Greiling
{"title":"High speed LSI technologies challenging the CMOS VLSI era","authors":"P. Greiling","doi":"10.1109/ISSCC.1985.1156842","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156842","url":null,"abstract":"The dominant VLSI technology for the next decade will be CMOS. Emerging technologies such as GaAs FETs, AlGaAs high electron mobility transistors, AlGaAs heterojunction bipolar transistors and Si bipolar transistors are all attempting to demonstrate performance advantages and specialized applications for each technology . . . The panel will address the potential role of these niche technologies in a CMOS VLSI dominated era.","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124412071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 25ns 16K CMOS PROM using a 4-transistor cell 使用4晶体管单元的25ns 16K CMOS PROM
1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156754
S. Pathak, J. Kupec, C. Murphy, D. Sawtelle, R. Shrivastava, F. Jenne
{"title":"A 25ns 16K CMOS PROM using a 4-transistor cell","authors":"S. Pathak, J. Kupec, C. Murphy, D. Sawtelle, R. Shrivastava, F. Jenne","doi":"10.1109/ISSCC.1985.1156754","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156754","url":null,"abstract":"A 25ns, 250mW, 2K×8 PROM using 1.2μ N-well CMOS technology will be described. Speed and programmability have been optimized by separating read and write transistors in a 4-transistor differential cell. A substrate bias generator raises the latchup immunity to over 200mA.","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121042440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
The 1984 semiconductor chip protection act 1984年的半导体芯片保护法案
1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156823
I. Ostroff
{"title":"The 1984 semiconductor chip protection act","authors":"I. Ostroff","doi":"10.1109/ISSCC.1985.1156823","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156823","url":null,"abstract":"","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121258139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low temperature CMOS 8 × 8b multipliers with sub 10ns speeds 低温CMOS 8 × 8b乘法器,速度低于10ns
1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156789
S. Hanamura, M. Aoki, T. Masuhara, O. Minato, Y. Sakai, T. Hayashida
{"title":"Low temperature CMOS 8 × 8b multipliers with sub 10ns speeds","authors":"S. Hanamura, M. Aoki, T. Masuhara, O. Minato, Y. Sakai, T. Hayashida","doi":"10.1109/ISSCC.1985.1156789","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156789","url":null,"abstract":"Low temperature CMOS (CRYO-CMOS) has been found to be especially suitable for VLSI based systems since it offers high density and low power dissipation. This paper will report on the performance of CRYO-CMOS 8×8b multipliers with 8ns multiplication time, and 5mW and 460mW power dissipation, respectively.","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122831526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 20ns static column 1Mb DRAM in CMOS technology 采用CMOS技术的20ns静态列1Mb DRAM
1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156769
K. Sato, H. Kawamoto, K. Yanagisawa, T. Matsumoto, S. Shimizu, R. Hori
{"title":"A 20ns static column 1Mb DRAM in CMOS technology","authors":"K. Sato, H. Kawamoto, K. Yanagisawa, T. Matsumoto, S. Shimizu, R. Hori","doi":"10.1109/ISSCC.1985.1156769","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156769","url":null,"abstract":"RECENT DEMANDS FOR DRAMs involve not only LSI, but high-speed column functions with reduced power consumption. This performance can best be accomplished by CMOS because of its low power dissipation and high-speed characteristics. This paper will report the development of a 1Mb static column DRAM using a back bias generator in N-well CMOS technology, with a column address access time of 20ns, a RAS access time of less than 80ns, and power dissipation of 230mW at 210ns cycle time. A photomicrograph of the chip is shown in Figure 1. The cell size is 3 . 3 5 ~ x 7.2p (=24.12p2) using a Corrugated Capacitor Cell (CCC)’. Die size is 4.68mm x 10.lmm (=47.3mm2) assembled in a 300-mil wide 18-pin DIP; Figure 2. The pin arrangement is also shown in this illustration. In the array memory, a folded-bit-line structure has been used with horizontal metal bit and vertical polycide word lines. The array consists of 16 identical blocks on a P-type substrate, with each block halved by sense amplifiers to reduce bit line capacitance, without increasing the width of the chip. Forming column select signals with a second aluminum layer is also useful in a multi-divided bit line structure’, because no additional column decoders are necessary. The bit line-to-cell capacitance ratio resulting from this multi-divided bit line structure is about 6, producing a total sensing signal of 600mV, with a boosted word line; Figure 3. A half Vcc bit line equalization precharging method* was used for low power consumption of the bit lines. The column circuits, shown in Figure 4, are designed to operate in a high speed static column mode. Therefore, CMOS circuitry is used for static operation. Moreover, the address transition detection (ATD) technique was adopted t o reduce the power dissipation at long cycle times. The ATD clock activates a column driver clock (h), a column select signal (YS), and a main amplifier, for a period of time. The ATD control of YS is demonstrated in Figure 3. Typical measured RAS and static column access times are shown in Figure 5 ; RAS access time is 74ns and static column access time is 20ns at a static column cycle (t/sc) of 20ns. The typical active power dissipa-_","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"580 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123073729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
A 2.2GHz transmission gate GaAs shift register 一种2.2GHz传输门GaAs移位寄存器
1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156832
M. Namordi, P. Newman, A. Cappon, L. Hanes, H. Statz
{"title":"A 2.2GHz transmission gate GaAs shift register","authors":"M. Namordi, P. Newman, A. Cappon, L. Hanes, H. Statz","doi":"10.1109/ISSCC.1985.1156832","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156832","url":null,"abstract":"The development of a 8b GaAs shift register employing transmission gates operating at clock rates up to 2.2GHz will be discussed. Low speed operation down to 1MHz has been demonstrated.","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132616353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An NMOS digital signal processor with multiprocessing capability 具有多处理能力的NMOS数字信号处理器
1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156830
S. Magar, D. Essig, E. Caudel, S. Marshall, R. Peters, K. Kneib
{"title":"An NMOS digital signal processor with multiprocessing capability","authors":"S. Magar, D. Essig, E. Caudel, S. Marshall, R. Peters, K. Kneib","doi":"10.1109/ISSCC.1985.1156830","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156830","url":null,"abstract":"This paper will describe a second generation 8-13MIP multi-tasking DSP with a 544×16b RAM and single cycle multiply/accumulation instructions. The chip is implemented with 2.4μ NMOS technology.","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128164143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 565/680Mb/s multiple coder/decoder for optical fiber trunk line systems 用于光纤干线系统的565/680Mb/s多路编/解码器
1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156792
I. C. Wood, M. Mudd, D. Taylor, P. Saul
{"title":"A 565/680Mb/s multiple coder/decoder for optical fiber trunk line systems","authors":"I. C. Wood, M. Mudd, D. Taylor, P. Saul","doi":"10.1109/ISSCC.1985.1156792","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156792","url":null,"abstract":"This report will cover a standard cell approach with triple layer metal to realize a data-rate conversion circuit for a 565/680Mb/s data Codec. CML logic has been used to achieve an aggregate data rate of 140Mb/s.","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127516026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Alpha particle effects on bipolar ECL static arrays 双极ECL静态阵列的α粒子效应
1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156869
S. Voldman, L. Patrick, D. Wong
{"title":"Alpha particle effects on bipolar ECL static arrays","authors":"S. Voldman, L. Patrick, D. Wong","doi":"10.1109/ISSCC.1985.1156869","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156869","url":null,"abstract":"This paper will discuss results obtained between experimental studies and circuit simulation of the soft error rates versus critical charge in static bipolar ECL memory arrays. Design optimization and process innovation was used to achieve failure rates below 0.1 fails/bit/Khr with critical charge exceeding 300fC.","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117216829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
System applications and limitations of submicron MOS 亚微米MOS的系统应用与限制
1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156848
I. Mack, F. Gaensslen
{"title":"System applications and limitations of submicron MOS","authors":"I. Mack, F. Gaensslen","doi":"10.1109/ISSCC.1985.1156848","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156848","url":null,"abstract":"MOS technology has progressed to where 1μ design rules can be supported. However, a question arises as to the appropriate effort which sould be applied to submicron MOS technology at this time to achieve the projected 20-30 times increase in device density and concomitant increase in system performance. The process, device and system implications of pursuing submicron MOS technology will be discussed.","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121207301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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