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1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers最新文献

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A full duplex 1200/300b/s single-chip CMOS modem 全双工1200/300b/s单片CMOS调制解调器
1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156849
G. Shapiro, A. Pindar, P. Kwok
{"title":"A full duplex 1200/300b/s single-chip CMOS modem","authors":"G. Shapiro, A. Pindar, P. Kwok","doi":"10.1109/ISSCC.1985.1156849","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156849","url":null,"abstract":"","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"346 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116490663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 50ns 48-term erasable programmable logic array 50ns 48期可擦可编程逻辑阵列
1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156773
R. Leung, S.M. Lee
{"title":"A 50ns 48-term erasable programmable logic array","authors":"R. Leung, S.M. Lee","doi":"10.1109/ISSCC.1985.1156773","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156773","url":null,"abstract":"This paper will cover the design of a CMOS EPROM process that serves to implement a 48 P-term AND-OR array with 16 inputs and 8 outputs. The array requires a 20mA quiescent current and 50mA maximum during switching and can be programmed using a conventional 21V EPROM programmer.","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122038884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A single chip 80b floating point processor 单片80b浮点处理器
1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156738
K. Takeda, F. Ishino, Y. Ito, R. Kasai, T. Nakashima
{"title":"A single chip 80b floating point processor","authors":"K. Takeda, F. Ishino, Y. Ito, R. Kasai, T. Nakashima","doi":"10.1109/ISSCC.1985.1156738","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156738","url":null,"abstract":"The application of 1.2μ N-well CMOS technology in a 5.6 MFLOP 80b floating-point processor chip will be described. The chip, which includes 50K gates and 15Kb of memory, was designed, in 11 man months with a heirarchical design automation system.","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125473289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 20ns color lookup table for raster scan displays 用于光栅扫描显示的20ns颜色查找表
1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156828
G. Work, G. Talbot, A. Ferris, N. Henderson, P. McGuinness
{"title":"A 20ns color lookup table for raster scan displays","authors":"G. Work, G. Talbot, A. Ferris, N. Henderson, P. McGuinness","doi":"10.1109/ISSCC.1985.1156828","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156828","url":null,"abstract":"A pipelined 20ns color lookup table with a microprocessor interface, implemented by a 1.75μ P well CMOS process will be discussed. Chip supports 8 planes of screen memory and produces 6b RGB DAC outputs.","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131694049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 10µW standby power 256K CMOS SRAM 一个10µW待机功率256K CMOS SRAM
1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156780
Y. Kobayashi, H. Eguchi, O. Kudoh, T. Hara, H. Ooka, I. Sasaki, M. Andoh, M. Tameda
{"title":"A 10µW standby power 256K CMOS SRAM","authors":"Y. Kobayashi, H. Eguchi, O. Kudoh, T. Hara, H. Ooka, I. Sasaki, M. Andoh, M. Tameda","doi":"10.1109/ISSCC.1985.1156780","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156780","url":null,"abstract":"This paper will report on a 55ns 256K CMOS SRAM that utilizes optimized poly load resistors, buried isolation and Ti polycide to achieve 10μW standby power in a 40.7mm2die.","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131782559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A CMOS facsimile video signal processor 一种CMOS传真视频信号处理器
1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156802
N. Hamada, M. Tadauchi, K. Nakashima, K. Yasunari, Y. Nagayama, N. Suemori
{"title":"A CMOS facsimile video signal processor","authors":"N. Hamada, M. Tadauchi, K. Nakashima, K. Yasunari, Y. Nagayama, N. Suemori","doi":"10.1109/ISSCC.1985.1156802","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156802","url":null,"abstract":"This paper will describe a facsimile video signal processor that incorporates a 4b flash A/D with an offset canceler to provide 5MHz performance. A 2.5μ CMOS chip contains 25,000 transistors and 840 bits of RAM and can control a CCD image scanner.","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131467263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 256K flash EEPROM using triple polysilicon technology 采用三重多晶硅技术的256K闪存EEPROM
1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156798
F. Masuoka, M. Asano, H. Iwahashi, T. Komuro, S. Tanaka
{"title":"A 256K flash EEPROM using triple polysilicon technology","authors":"F. Masuoka, M. Asano, H. Iwahashi, T. Komuro, S. Tanaka","doi":"10.1109/ISSCC.1985.1156798","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156798","url":null,"abstract":"This report will cover a 256K Flash Electrically Erasable PROM with a single transistor cell. Chip size of 5.7×5.8mm2was achieved by using 2.0μ design rules and triple polysilicon technology.","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131554021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
A 1Mb CMOS DRAM 1Mb CMOS DRAM
1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156770
H. Kirsch, D. Clemons, S. Davar, J. Harman, C. Holder, W. Hunsicker, F. Procyk, J. Stefany, D. Yaney, J. Petrizzi
{"title":"A 1Mb CMOS DRAM","authors":"H. Kirsch, D. Clemons, S. Davar, J. Harman, C. Holder, W. Hunsicker, F. Procyk, J. Stefany, D. Yaney, J. Petrizzi","doi":"10.1109/ISSCC.1985.1156770","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156770","url":null,"abstract":"THIS PAPER WILL DESCRIBE a 1Mb DRAM with a typical RE access time of 80ns. One mode of operation allows a 2Oblb/s data rate with relaxed system requirements*. A single 5V supply powers the devicywhich dissipates 160mW for a 260ns cycle. During standby (RE high), the dissipation is 0.5mW for TTL level inputs. The DRAM is packaged in an lbpin, 300-mil plastic DIP. A mask option allows the DIP pin out to meet either the proposed JEDEC standard or an evolutionary pattern which is more compatible with the standard 256K DRAM 16-pin package pin out. Circuit design, emphasizing reliability, provides limiting of maximum internal stress levels. The maximum voltage levels of boosted nodes are controlled;junctions are not operated near their breakdown voltages and transistors are not operated near punch through. This control is particularly important at high Vcc levels.","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132104572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A 256K CMOS SRAM with variable-impedance loads 具有可变阻抗负载的256K CMOS SRAM
1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156873
S. Yamamoto, K. Uchibori, K. Nagasawa, S. Meguro, T. Yasui, O. Minato, T. Masuhara
{"title":"A 256K CMOS SRAM with variable-impedance loads","authors":"S. Yamamoto, K. Uchibori, K. Nagasawa, S. Meguro, T. Yasui, O. Minato, T. Masuhara","doi":"10.1109/ISSCC.1985.1156873","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156873","url":null,"abstract":"A 45ns 256K (32K×8b) CMOS SRAM with a 200mW at 10MHz active power dissipation will be described. The RAM utilizes variable impedance data-line loads, pulsed word lines and latched output buffers. A polycide vss-line is used in a 95μm2memory cell.","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130802219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A 480 × 400 element image sensor with a charge sweep device 480 × 400元图像传感器与电荷扫描装置
1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156786
M. Kimata, M. Denda, N. Yutani, N. Tsubouchi
{"title":"A 480 × 400 element image sensor with a charge sweep device","authors":"M. Kimata, M. Denda, N. Yutani, N. Tsubouchi","doi":"10.1109/ISSCC.1985.1156786","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156786","url":null,"abstract":"A description of a vertical charge transfer that makes it possible to narrow the channel width to the size of the lithographic limit without degradation of charge handling capacity of the vertical charge transfer will be presented. The array size of the imager sensor with a 1/2\" format is 480(V)×400(H) and the pixel size is10×16μ^{2}.","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130928543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
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