1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers最新文献

A CML GaAs 4Kb SRAM

1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1985-12-01 DOI: 10.1109/ISSCC.1985.1156859

K. Takahashi, T. Maeda, F. Katano, T. Furutsuka, A. Higashisaka

引用次数: 3

A 4.5ns 256K CMOS SRAM with tri-level word line 4.5ns 256K三电平字线CMOS SRAM

1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1985-12-01 DOI: 10.1109/ISSCC.1985.1156744

H. Shinohara, K. Anami, K. Ichinose, T. Wada, Y. Kohno, Y. Kawai, Y. Akasaka, S. Kayano

引用次数: 7

Differential split-level CMOS logic for sub-nanoseconds speeds 用于亚纳秒速度的差分分电平CMOS逻辑

1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1985-10-01 DOI: 10.1109/ISSCC.1985.1156827

L. Pfennings, W. Mol, J. Bastiaens, J. V. van Dijk

引用次数: 55

Integrated services digital network line termination chip set 综合业务数字网线路终端芯片组

1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156791

M. Rahier, D. Sallaerts, R. Dierckx

引用次数: 1

Multigigabit/second silicon decision circuit 多千兆位/秒硅判决电路

1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156778

D. Clawin, U. Langmann

{"title":"Multigigabit/second silicon decision circuit","authors":"D. Clawin, U. Langmann","doi":"10.1109/ISSCC.1985.1156778","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156778","url":null,"abstract":"IMPLEMENTATIONS OF MONOLITHIC decision circuits for multigigabit communication systems have been based, in the main, on GaAs technology”’. Recently, a silicon decision circuit using a 0.5p bipolar process3 was reported. This paper will describe a monolithic silicon bipolar decision circuit using rather conventional 2.5p emitter stripe widths and pn-junction isolation, that may be extended into the multigigabit/ second range4. The architecture, implementation and experimental results will be covered. The common approach to a decision circuit is a masterslave D-flip flop. Commercially available silicon D-flip flops can be operated, at best, up to lGh/s. This range has now been extended to 1 .5Gb/s5. The bit rate can be increased by parallel operation4. The proposed decision circuit consists mainly of two identical flip flops, as illustrated in the functional block and the circuit diagrams. of Figure l a and b. The upper and the lower flip flops are operated in a complementary mode. They are enabled alternately by current switches in a series-gating configuration controlled by a sinusoidal clock. This mode of operation results in a demultiplexing of the input signal into two bit streams at half the bit rate, shifted in phase by half a clock cycle. A 2:l-multiplexer interleaves the two bit streams into one signal of the full bit rate. Thus, critical master-slave D-flip flop operation is required at only half the clock frequency for each bit stream.","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123559000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

A 95ns 256k CMOS EPROM 一个95ns 256k CMOS EPROM

1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156795

K. Yoshizaki, H. Takahashi, Y. Kamigaki, T. Yasui, K. Komori, H. Katto

引用次数: 2

Video signal processing 视频信号处理

1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/isscc.1985.1156779

R. van de Plassche

引用次数: 0

64Kb ECL RAM with redundancy 具有冗余的64Kb ECL RAM

1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156836

Y. Okajima, K. Toyoda, T. Awaya, K. Tanaka, Y. Nakamura

{"title":"64Kb ECL RAM with redundancy","authors":"Y. Okajima, K. Toyoda, T. Awaya, K. Tanaka, Y. Nakamura","doi":"10.1109/ISSCC.1985.1156836","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156836","url":null,"abstract":"A 64Kw x l b bipolar ECL RAM with two-array redundancy will be described. This device, using a PNP load cell, was fabricated in IOP-I1 (second generation of Isolation by Oxide and Polysilicon) and 1 . 2 ~ lithography. A redundant circuit configuration was applied to the RAM, without deterioration of the high speed characteristics of ECL. Decoder circuits with jun,ction shorting PROM, can be reliably programmed, and enhance yield, as much as the present.16Kb ECL RAM. Two spare arrays were prepared for row and column; Figure 1. The speed of the spare arrays for decoding has been found to be equivalent to that provided by ordinary decoders, because the only dc high or low voltages to the compare gates are generated by the PROM circuit. But this additional redundant circuit increases the number of peripheral gates and the power dissipation. To overcome this problem, the following circuits were introduced: ( I ) a low power second stage column decoder (most of the unselected driver gates do not require current flow for low output levels); (2) a Darlington word driver with pull down resistance (the high current gain of the Darlington transistor decreases the power of word driver gates); Figure 2. The PNP load cell, includes a P-type deep emitter and collector for fast write switching: additionally, the cell affords control of the beta of the read/write transistor for a decrease of the parasitic sink current’. These diffusions have been merged into a single P-type step (Figure 3) which shortens masking steps and reduces cell area. Fine line 1.2p lithography has also been employed. The minimum emitter size is 1 .21 x 2.41 and the minimum linewidth plus spacing of the first and second metal layers are 4 . 0 ~ and 5 . 0 ~ respectively. Isolation width is 2.4F Cell area is 52412, while die size is 55.4mm2. A typical address access time of lOns has been obtained. Figure 4 shows switching waveforms of the address input and data output. A microphotograph of the chip is shown in Figure 5. Characteristic features of this RAM and typical transistor parameters are summarized on Tables 1 and 2. By applying 1.01 lithography, sub lOns performance is expected.","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122628705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 21

A 5µs 10b CMOS ADC with track-and-hold 5µs 10b CMOS ADC，跟踪保持

1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156781

T. Doluca, P. Parvarandeh

引用次数: 1

An 8Kb content-addressable and reentrant memory 8Kb的内容可寻址和可重入内存

1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156820

H. Kodata, J. Miyake, Y. Nishimichi, H. Kudo, K. Kagawa

引用次数: 8