1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers最新文献_第2页

A 100ns 256K CMOS EPROM

1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156796

H. Gaw, E. Hokelek, M. Holler, S. Lee, L. Olson, M. Reitsma, H. So, K. Tam, M. Van Buskirk

引用次数: 9

CMOS video filters using switched capacitor 14MHz circuits CMOS视频滤波器使用开关电容14MHz电路

1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156862

K. Matsui, T. Matsuura, S. Fukasawa, Y. Izawa, Y. Toba, N. Miyake, K. Nagasawa

引用次数: 4

An 80ps 2500-gate bipolar macrocell array 一个80ps 2500门双极宏细胞阵列

1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156752

S. Horiguchi, M. Suzuki, H. Ichino, S. Konaka, T. Sakai

引用次数: 20

A 42ps 2K-gate GaAs gate array 一种42ps 2k栅极GaAs栅极阵列

1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156841

N. Toyoda, N. Uchitomi, Y. Kitaura, M. Mochizuki, K. Kanazawa, T. Terada, Y. Ikawa, A. Hojo

{"title":"A 42ps 2K-gate GaAs gate array","authors":"N. Toyoda, N. Uchitomi, Y. Kitaura, M. Mochizuki, K. Kanazawa, T. Terada, Y. Ikawa, A. Hojo","doi":"10.1109/ISSCC.1985.1156841","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156841","url":null,"abstract":"TO INCREASE speed of microelectronic systems, it is the interchip signal delay that should be reduced by maximizing the integration level. As the integration level increases, however, the development time becomes longer. The rapid development of LSIs is increasingly important because the product life cycle has been becoming shorter. A gate array approach is effective under these circumstances. Very high-speed ICs such as Si bipolar ECL logic, is no exception, and 2.5-5.0K gate gate arrays with 0.35-0.5011s loaded gate delay have been developed. However, very large power consumption, 5-8W/chip, limit their field of application. GaAs gate arrays have attracted interest as a replacement for the Si ECL gate array because of the smaller gate delay and lower power consumption. To date, several types of GaAs gate array have been reported’ ’2’3. This paper will describe a 2K-gate DCFL (Direct Coupled FET Logic) GaAs gate array with a 42ps unloaded and 215ps loaded gate delay at a power dissipation of 0.5mW/gate. An 8 x 8 b parallel multiplier has been fabricated on this chip. A multipiication time of 8.5ns was achieved at a power dissipation of 400mW, an improvement over an 8 x 8b Si ECL multiplier with custom design . The current design also consumes about 35Yo less power.","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114323050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

A 1.2GHz frequency synthesizer using a GaAs 20/21/22/23/24 modulus divider 采用GaAs 20/21/22/23/24模分频器的1.2GHz频率合成器

1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156870

M. Rocchi, B. Chantepie, B. Gabillard, G. Haldemann, J. Debost, J. Andrieux, F. Robert

引用次数: 0

A switched capacitor stereo decoder 开关电容立体声解码器

1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156865

A. Roermund, P. Coppelmans, J. Hendrickx, D. Logie

引用次数: 3

A 2K × 9 dual port memory 2K × 9双端口内存

1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156787

F. Barber, D. Eisenberg, G. Ingram, M. Strauss, T. Wik

引用次数: 5

An opamp with 375Vµs slew rate, ±100mA output current 输出电流为±100mA，转换速率为375Vµs的运放

1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156722

G. Cotreau

引用次数: 1

MOS ADC-filter combination that does not require precision analog components MOS adc -滤波器组合，不需要精密模拟元件

1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156834

M. Hauser, P. Hurst, R. Brodersen

{"title":"MOS ADC-filter combination that does not require precision analog components","authors":"M. Hauser, P. Hurst, R. Brodersen","doi":"10.1109/ISSCC.1985.1156834","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156834","url":null,"abstract":"AN OVERSAMPLE-AND-DECIMATE ARCHITECTURE yielding a analog-to-digital interface system with a built-in maskprogrammable digital antialias filter in standard 5V digital MOS technology will be reported. Unlike other MOS A/D converter techniques, this approach requires no precision component ratios or precision comparator, nor a double-polysilicon or other special capacitor structure. Prototype devices display approximately 12b converter linearity at an 8kHz output rate with a single 5V power supply and a total die area of 4 8mm? The low supply voltage and simplified process requirements are attractive for scaled MOS fabrication technologies. This is intended as a linear (non-companding) analog-interface block for constant-sampling-rate applications uch as speech processing. The system is based on l b A/D conversion, downsampled 256 times by a 1024-point, finite-impulse-response (FIR) digital lowpass filter. Such a configuration can display a net resolution exceeding the performance of the internal analog components, and since the bulk of the circuitry is digital, it benefits from continued technology scalmg. It differs also from interpohtiue A/D circuits’, in that it requires no internal D/A converter, nor does it produce a coarser quantization with larger inputs. A delta-sigma-modulator front end, used elsewhere in disCrete2, bipolar3 and passive grounded-capacitor MO!? circuitry, has been realized with a parasitic-insensitive switchedcapacitor integrator; Figure 1. The parasitic insensitivity allows","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"XXVIII 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128839330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 64

A 128 EPROM with encrypted read access 具有加密读访问的128 EPROM

1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156818

A. Folmsbee, D. Hoff, L. Letham

引用次数: 1