1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers最新文献

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Design and simulation of self-aligned modulation doped AlGaAs/GaAs ICs 自对准调制掺杂AlGaAs/GaAs集成电路的设计与仿真
1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156868
M. Shur, Tzu-Hung Chen, C. Hyun, P. Jenkins
{"title":"Design and simulation of self-aligned modulation doped AlGaAs/GaAs ICs","authors":"M. Shur, Tzu-Hung Chen, C. Hyun, P. Jenkins","doi":"10.1109/ISSCC.1985.1156868","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156868","url":null,"abstract":"Device design and simulation techniques for optimizing the performance of MODFET ICs will be presented. Self-aligned ion-implanted MODFETs with transconductances up to 249mmhos/mm and ring oscillators with 17.6ps propagation delay have been fabricated.","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"3588 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127523513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A family of CMOS compatible bandgap references 一个家族的CMOS兼容带隙参考
1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156737
M. Degrauwe, E. Vittoz, H. Oguey, O. Leuthold
{"title":"A family of CMOS compatible bandgap references","authors":"M. Degrauwe, E. Vittoz, H. Oguey, O. Leuthold","doi":"10.1109/ISSCC.1985.1156737","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156737","url":null,"abstract":"CMOS voltage references, which make use of compatible lateral bipolar transistors, will be described. The circuits are insensitive to low current gain of these devices and to amplifier offset. The output reference voltage is reproducible within 2mV, over the commercial temperature range, when all of the circuits of the same batch are trimmed at a single temperature.","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130259881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A bi-fet operational amplifier with 400ns settling time 具有400ns稳定时间的双场效应运算放大器
1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156819
R. Russel, J. Moyer
{"title":"A bi-fet operational amplifier with 400ns settling time","authors":"R. Russel, J. Moyer","doi":"10.1109/ISSCC.1985.1156819","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156819","url":null,"abstract":"This paper will describe a 15MHz 30V/μs slew rate operational amplifier which settles to .01% in 400ns for a 10V step. The offset is internally trimmed to 250μV without affecting temperature drift.","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126712942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A collinear 3-chip image sensor 共线3芯片图像传感器
1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156739
T. Aoki, H. Nakatani, M. Kojima, S. Ohashi, I. Teramoto, H. Mizuno
{"title":"A collinear 3-chip image sensor","authors":"T. Aoki, H. Nakatani, M. Kojima, S. Ohashi, I. Teramoto, H. Mizuno","doi":"10.1109/ISSCC.1985.1156739","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156739","url":null,"abstract":"This report will cover a collinearly arranged multi-chip constant-type CCD linear image sensor that can read an A4 size document with the resolution of 16 lines/mm. A s/n ratio as high as 48dB was obtained at 0.0051x's exposure of a green fluorescence lamp, where the photoresponse nonuniformity was less than ±5%.","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126388854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 470MHz 5V CATV tuner 470MHz 5V有线电视调谐器
1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156746
C. Yamada, Y. Ueki, M. Itoh, A. Satoh, K. Ohya
{"title":"A 470MHz 5V CATV tuner","authors":"C. Yamada, Y. Ueki, M. Itoh, A. Satoh, K. Ohya","doi":"10.1109/ISSCC.1985.1156746","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156746","url":null,"abstract":"A conversion gain of 24dB and cross modulation of -19dBm, achieved in the design of a CATV tuner, will be discussed. An ac-coupled IF amplifier provides a 1dB compression level of +10dBm.","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115275716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A LAN system interface chip with selectable bus protocols 具有可选总线协议的局域网系统接口芯片
1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156768
D. Walters, P. Lou, O. Fanini, P. Koeppen
{"title":"A LAN system interface chip with selectable bus protocols","authors":"D. Walters, P. Lou, O. Fanini, P. Koeppen","doi":"10.1109/ISSCC.1985.1156768","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156768","url":null,"abstract":"THE DESIGN OF A CHIP providing interface to a VLSI chip set implementing an IEEE802.5 compatible Local Area Network (LAN) adapter will be described. The chip set’ includes pairs of VLSI and MSI media interface chips. The attaching system bus can be microprocessor compatible, eight or sixteen bits wide, and either synchronous or asychronous. The chip’s buffered DMA channel supports 5Mb/s peak bandwidth, 24b system addresses, cycle steal and burst modes, bus error, bus release, and communication between digital systems with different byte addressing conventions’. Other features include a system memory-mapped window allowing read/write access to the adapter memory, and a communication port with command and status registers supporting interrupts and interrupt knowledge vectoring. The logic generates parity for address and data bytes, and provides parity error handling options. Test modes assist both device stuck fault test coverage and board level testing. A block diagram of the chip is shown in Figure 1. A 5V, 2 . 4 ~ NMOS technology with single metal and polysilicon interconnect levels was used to fabricate the design on an epitaxial P on P+ substrate. Metal width sizing of interconnect for supplies and critical signals supports a 40,000-hour power-on reliability requirement. The substrate is biased at -2V by two integrated charge pumps placed on opposite sides of the chip. Logic is incorporated into the chip to protect output buffers by asserting an internal reset signal in the event that any of the input clocks should fail to oscillate while power is applied. A 104K square mil die (Figure 4) is packaged in a 100-pin grid array, and contains 18.6K transistors that were laid out and designed with custom and automated3 methods. High-speed synchronizers condition asychronous system bus signals to the chip’s internal clock system. To enhance reliability, the synchronizers were designed to minimize propagation delay, maximize time available for outputs to achieve valid logic levels, and to avoid disturbing the feedback system within the resolution time. Logic receiving synchronizer outputs has been","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"146 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122610873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
15MHz CMOS switched capacitor filters 15MHz CMOS开关电容滤波器
1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156872
D. Ribner, M. Copeland, M. Milkovic
{"title":"15MHz CMOS switched capacitor filters","authors":"D. Ribner, M. Copeland, M. Milkovic","doi":"10.1109/ISSCC.1985.1156872","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156872","url":null,"abstract":"Fully differential and single-ended switched filters implemented in 1.25μ CMOS will be described. Passbands have been achieved within 0.1db of design for 10MHz clocks and 2dB for 15MHz clocks. Fully differential opamps used exhibit a 70MHz gain-bandwidth product, 100V/μs slew rate and a current drain of 215μA.","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"227 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122616647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A 64K EEPROM with extended temperature and page mode operation 具有扩展温度和页面模式操作的64K EEPROM
1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156797
P. Suciu, M. Briner, C. Bill, D. Rinerson
{"title":"A 64K EEPROM with extended temperature and page mode operation","authors":"P. Suciu, M. Briner, C. Bill, D. Rinerson","doi":"10.1109/ISSCC.1985.1156797","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156797","url":null,"abstract":"A1.8muN channel 64K EEPROM with temperature operation from -55°C to +125°C will be described. Page mode allows writing of 32bytes in 10μs.","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"XXVIII 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131179505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 1.5µCMOS gate array with configurable ROM and RAM 具有可配置ROM和RAM的1.5µCMOS门阵列
1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156783
M. Ueda, K. Sakashita, R. Yonezu, T. Fujimura, T. Arakawa, S. Asai, Y. Kuramitsu
{"title":"A 1.5µCMOS gate array with configurable ROM and RAM","authors":"M. Ueda, K. Sakashita, R. Yonezu, T. Fujimura, T. Arakawa, S. Asai, Y. Kuramitsu","doi":"10.1109/ISSCC.1985.1156783","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156783","url":null,"abstract":"The use of 1.5μ CMOS technology to implement a 8000 equivalent gate array with double word line memory addressing on a 9.9×9.8mm2chip will be discussed. Describe, too, will be the implementation and operation of a 16b micro-processor with 1024b ROM and 256b RAM.","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124834240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
CAE work stations CAE工作站
1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156847
I. Getreu, R. Streiber
{"title":"CAE work stations","authors":"I. Getreu, R. Streiber","doi":"10.1109/ISSCC.1985.1156847","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156847","url":null,"abstract":"Computer-aided engineering work stations have become very popular in the electronic press. Many claims have been made, but little has been heard from the user's view . . . This panel will concentrate on the user's requirements. Some of the questions that will be addressed are: the actual functions of the work stations and their usefulness and limitations, user experiences, the future role of the stations and effect on designing, developments that could contribute to effectiveness of the stations, which designers are aided by the work station and who have no need for them, how should works stations be used and configured and the cost effectiveness of the stations.","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132092361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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