A 42ps 2K-gate GaAs gate array

Abstract

TO INCREASE speed of microelectronic systems, it is the interchip signal delay that should be reduced by maximizing the integration level. As the integration level increases, however, the development time becomes longer. The rapid development of LSIs is increasingly important because the product life cycle has been becoming shorter. A gate array approach is effective under these circumstances. Very high-speed ICs such as Si bipolar ECL logic, is no exception, and 2.5-5.0K gate gate arrays with 0.35-0.5011s loaded gate delay have been developed. However, very large power consumption, 5-8W/chip, limit their field of application. GaAs gate arrays have attracted interest as a replacement for the Si ECL gate array because of the smaller gate delay and lower power consumption. To date, several types of GaAs gate array have been reported’ ’2’3. This paper will describe a 2K-gate DCFL (Direct Coupled FET Logic) GaAs gate array with a 42ps unloaded and 215ps loaded gate delay at a power dissipation of 0.5mW/gate. An 8 x 8 b parallel multiplier has been fabricated on this chip. A multipiication time of 8.5ns was achieved at a power dissipation of 400mW, an improvement over an 8 x 8b Si ECL multiplier with custom design . The current design also consumes about 35Yo less power.