64Kb ECL RAM with redundancy

Abstract

A 64Kw x l b bipolar ECL RAM with two-array redundancy will be described. This device, using a PNP load cell, was fabricated in IOP-I1 (second generation of Isolation by Oxide and Polysilicon) and 1 . 2 ~ lithography. A redundant circuit configuration was applied to the RAM, without deterioration of the high speed characteristics of ECL. Decoder circuits with jun,ction shorting PROM, can be reliably programmed, and enhance yield, as much as the present.16Kb ECL RAM. Two spare arrays were prepared for row and column; Figure 1. The speed of the spare arrays for decoding has been found to be equivalent to that provided by ordinary decoders, because the only dc high or low voltages to the compare gates are generated by the PROM circuit. But this additional redundant circuit increases the number of peripheral gates and the power dissipation. To overcome this problem, the following circuits were introduced: ( I ) a low power second stage column decoder (most of the unselected driver gates do not require current flow for low output levels); (2) a Darlington word driver with pull down resistance (the high current gain of the Darlington transistor decreases the power of word driver gates); Figure 2. The PNP load cell, includes a P-type deep emitter and collector for fast write switching: additionally, the cell affords control of the beta of the read/write transistor for a decrease of the parasitic sink current’. These diffusions have been merged into a single P-type step (Figure 3) which shortens masking steps and reduces cell area. Fine line 1.2p lithography has also been employed. The minimum emitter size is 1 .21 x 2.41 and the minimum linewidth plus spacing of the first and second metal layers are 4 . 0 ~ and 5 . 0 ~ respectively. Isolation width is 2.4F Cell area is 52412, while die size is 55.4mm2. A typical address access time of lOns has been obtained. Figure 4 shows switching waveforms of the address input and data output. A microphotograph of the chip is shown in Figure 5. Characteristic features of this RAM and typical transistor parameters are summarized on Tables 1 and 2. By applying 1.01 lithography, sub lOns performance is expected.