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1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers最新文献

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A 750MS/s NMOS latched comparator 一个750MS/s的NMOS锁存比较器
1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156729
D. Soo, A. Voshchenkov, G. Chin, V. Archer, M. Lau, M. Morris, P. Ko, R. Meyer, B. Wooley
{"title":"A 750MS/s NMOS latched comparator","authors":"D. Soo, A. Voshchenkov, G. Chin, V. Archer, M. Lau, M. Morris, P. Ko, R. Meyer, B. Wooley","doi":"10.1109/ISSCC.1985.1156729","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156729","url":null,"abstract":"THIS PAPER WILL DESCRIBE THE DESIGN of analog circuits integrated in a polysilicon gate NMOS technology with lp effective channel length devices’. In particular, a latched comparator with 4b input resolution at 750MS/s and a wideband amplifier with l0dB of voltage gain over a bandwidth of 1.25GHz, when driving 130fF of on-chip capacitance, will be reported. The comparator was designed primarily for application to high-speed flash A/D conversion, but is is also suitable for use in integrated broadband fiber optic receivers. Its circuit configuration differs from previous in that negative feedback is used in the preamplifier section to trade gain for bandwidth.","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114936611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Nonvolatile circuits as building blocks 非易失性电路作为构建模块
1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156851
P. Salsbury
{"title":"Nonvolatile circuits as building blocks","authors":"P. Salsbury","doi":"10.1109/ISSCC.1985.1156851","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156851","url":null,"abstract":"PROMs and EEPROMs, which have become established as standard forms of memory, are also moving beyond the boundries of traditional memory organizations. They are being used as reprogrammable, nonvolatile building blocks within microcomputers, logic arrays and custom circuits. In a sense, these building blocks form the heart of a family of circuits that can \"learn and remember\". Issues that face both the designer and end user of these VLSI circuits include field reliability, testability, cost/benefit tradeoffs and the choice of technical approach. Panelists will describe their views on nonvolatile functions within their own applications, describing design requirements, comparing with competing approaches, and forecasting the direction of future forms of non-volatile circuits.","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"451 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115286698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 5V 10A CMOS/PNP linear regulator 5V 10A CMOS/PNP线性稳压器
1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156736
R. Wrathall
{"title":"A 5V 10A CMOS/PNP linear regulator","authors":"R. Wrathall","doi":"10.1109/ISSCC.1985.1156736","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156736","url":null,"abstract":"This paper will report on a monolithic 5V 10A linear voltage regulator using metal gate CMOS and a vertical PNP output transistor. The chip includes thermal and over current protection circuits.","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115374764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 90ns 1Mb DRAM with multi-bit test mode 采用多比特测试模式的90ns 1Mb DRAM
1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156837
M. Kumanoya, K. Fujishima, K. Tsukamoto, Y. Nishimura, K. Saito, T. Matsukawa, T. Yoshihara, T. Nakano
{"title":"A 90ns 1Mb DRAM with multi-bit test mode","authors":"M. Kumanoya, K. Fujishima, K. Tsukamoto, Y. Nishimura, K. Saito, T. Matsukawa, T. Yoshihara, T. Nakano","doi":"10.1109/ISSCC.1985.1156837","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156837","url":null,"abstract":"A 1Mb DRAM using a half Vcc biased memory cell with a reduced electric field of 2MV/cm will be reported. A shared sense amplifier design and a continous nibble mode are also included. Additionally, a test pin allows testing as a 256K×4 memory. Die is 65mm2.","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"221 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122866202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
A 1ns 20K CMOS gate array series with configurable 15ns 12K memory 一个1ns 20K CMOS门阵列系列，可配置15ns 12K存储器
1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156742
Y. Takayama, S. Fujii, T. Tanabe, K. Kawauchi, T. Yoshida, K. Yamashita
{"title":"A 1ns 20K CMOS gate array series with configurable 15ns 12K memory","authors":"Y. Takayama, S. Fujii, T. Tanabe, K. Kawauchi, T. Yoshida, K. Yamashita","doi":"10.1109/ISSCC.1985.1156742","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156742","url":null,"abstract":"A CMOS array providing a maximum of 20,000 logic gates or logic and memory will be described. Typical gate delays of 1.0ns and memory access time of 15ns have been obtained using a 1.5μ twin tub process.","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123028031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 1.2GHz single-chip NMOS PLL 一种1.2GHz单片NMOS锁相环
1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156815
T. Yamada, S. Wada, S. Ito, Y. Suga
{"title":"A 1.2GHz single-chip NMOS PLL","authors":"T. Yamada, S. Wada, S. Ito, Y. Suga","doi":"10.1109/ISSCC.1985.1156815","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156815","url":null,"abstract":"The use of 1.8μ double LOCOS NMOS technology with an on-chip supply voltage converter for 1.2GHz single chip PLL will be reported. Basic application of the design is for digital tuning systems of TV receivers.","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125722924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
The 1984 Semiconductor chip protection act 1984年的《半导体芯片保护法》
1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/isscc.1985.1156751
{"title":"The 1984 Semiconductor chip protection act","authors":"","doi":"10.1109/isscc.1985.1156751","DOIUrl":"https://doi.org/10.1109/isscc.1985.1156751","url":null,"abstract":"","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126797178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A ± 0.75V opamp with rail-to-rail input/output range ±0.75V运放，轨对轨输入/输出范围
1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156743
J. Huijsing, D. Linebarger
{"title":"A ± 0.75V opamp with rail-to-rail input/output range","authors":"J. Huijsing, D. Linebarger","doi":"10.1109/ISSCC.1985.1156743","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156743","url":null,"abstract":"An opamp with a minimum supply voltage of ±0.75V and a bandwidth of 0.6MHz using a nested loop frequency compensation technique will be reported. Dual input stages are used to allow common mode operation at either supply rail.","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121654306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 490 × 404 element imager for a single chip color camera 用于单片彩色相机的490 × 404单元成像仪
1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156765
K. Horii, T. Kuruda, Y. Matsuda, T. Kuriyama, N. Mino, Y. Horoshima, T. Kunii, H. Mizuno
{"title":"A 490 × 404 element imager for a single chip color camera","authors":"K. Horii, T. Kuruda, Y. Matsuda, T. Kuriyama, N. Mino, Y. Horoshima, T. Kunii, H. Mizuno","doi":"10.1109/ISSCC.1985.1156765","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156765","url":null,"abstract":"A CCD imager with a 5.86mm(V) × 7.13mm(H) chip and an imaging area of 4.32mm(V) × 5.73mm(H) will be reported. The S/N ratio is 55dB under scene illumination level of 200 1x, which is 50% of the saturation illumination.","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121662117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Silicon bipolar 6.2G Hz 300mW frequency dividers 硅双极6.2G Hz 300mW分频器
1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1985.1156730
K. Onodera, A. Sawairi, Y. Hara, N. Kusama
{"title":"Silicon bipolar 6.2G Hz 300mW frequency dividers","authors":"K. Onodera, A. Sawairi, Y. Hara, N. Kusama","doi":"10.1109/ISSCC.1985.1156730","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156730","url":null,"abstract":"This paper will describe a divide-by-4 frequency divider for the local oscillator in a microwave communication system operating at 6.2GHz and dissipating 300mW. The circuit consists of self-aligned silicon bipolar transistors fabricated with 1.25μ lithography which have a cutoff frequency of 11GHz.","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133433697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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