A 750MS/s NMOS latched comparator

Abstract

THIS PAPER WILL DESCRIBE THE DESIGN of analog circuits integrated in a polysilicon gate NMOS technology with lp effective channel length devices’. In particular, a latched comparator with 4b input resolution at 750MS/s and a wideband amplifier with l0dB of voltage gain over a bandwidth of 1.25GHz, when driving 130fF of on-chip capacitance, will be reported. The comparator was designed primarily for application to high-speed flash A/D conversion, but is is also suitable for use in integrated broadband fiber optic receivers. Its circuit configuration differs from previous in that negative feedback is used in the preamplifier section to trade gain for bandwidth.