{"title":"A Winchester data path and servo signal processor family","authors":"J. Holt, A. Strong, E. Erwin, J. Frazee, D. Hu","doi":"10.1109/ISSCC.1985.1156777","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156777","url":null,"abstract":"This report will cover the use of one CMOS and two bipolar ICs to provide analog and digital signal processing for 25Mb/s Winchester disk drives. A single chip 25Mb/s data separator-encoder realizes both modified frequency modulation and","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128346346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A wafer with electrically programmable interconnections","authors":"H. Stopper","doi":"10.1109/ISSCC.1985.1156864","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156864","url":null,"abstract":"Wafer-scale ring oscillators interconnected on a 100mm silicon substrate using discretionary electrical programming of two metalization levels with amorphous silicon alloy 'anti-fuses' will be reported.","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128573555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Saigo, K. Niwa, T. Ohto, S. Kurosawa, T. Takada
{"title":"A triple-level wired 24K gate CMOS gate array","authors":"T. Saigo, K. Niwa, T. Ohto, S. Kurosawa, T. Takada","doi":"10.1109/ISSCC.1985.1156854","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156854","url":null,"abstract":"This paper will describe an array using adjacent double transistor columns and 2μ design rules for a 12.8×12.8mm2chip. Implementation of a digital signal processor with 19.3K gates of RAM, multiply, ALU and control logic will be compared with a full custom design.","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129117930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. De Muelenaere, J. Legat, P. Deleuze, P. Jespers
{"title":"A custom IC for image processing and recognition","authors":"P. De Muelenaere, J. Legat, P. Deleuze, P. Jespers","doi":"10.1109/ISSCC.1985.1156800","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156800","url":null,"abstract":"A 2MHz optical character recognition chip whose architecture can support algorithms for preprocessing, binarization and feature extraction will be reported. The chip (3.9mm× 7mm) was made with 6μm NMOS technology, and contains 13000 transistors. Dissipation is 300mW.","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"57 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133003548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 280ps Josephson 4b × 4b parallel multiplier","authors":"J. Sone, J. Tsai, S. Ema, H. Abe","doi":"10.1109/ISSCC.1985.1156724","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156724","url":null,"abstract":"A 4b×4b multiplier with 350ps multiplication time and 1mW dissipation that has been built with 249 resistor-coupled Josephson logic gates will be described. Circuits were fabricated in a Pb-alloy process with 5μ minimum line widths and junction diameters.","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129716811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A CMOS microprocessor with instruction-controlled register file and ROM","authors":"H. Maejima, H. Kida, T. Kihara, S. Baba, Y. Akao","doi":"10.1109/ISSCC.1985.1156871","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156871","url":null,"abstract":"This report will cover an 8b microcomputer implemented in 2μm rules. A reconfigurable RAM register file and direct instruction control of a ROM microprogram serves to facilitate redefinition of the instruction set.","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134097986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 4K CMOS gate array with automatically-generated test circuits","authors":"S. Kuboki, I. Masuda, T. Hayashi, S. Torii","doi":"10.1109/ISSCC.1985.1156857","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156857","url":null,"abstract":"A testable 4K CMOS array using a scan bus and a 2μ process on a 7.2×7.0mm2chip will be described. The cell structure and D/A system supports 98-100% dc fault testing without logic design restrictions in a chip area of 5%.","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132085889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Jolly, R. Tesch, K. J. Campbell, D. Tennant, J. Olund, B. Cremen, R. Lefferts, P. A. Andrews
{"title":"Two 35ns 64K CMOS EEPROMs","authors":"R. Jolly, R. Tesch, K. J. Campbell, D. Tennant, J. Olund, B. Cremen, R. Lefferts, P. A. Andrews","doi":"10.1109/ISSCC.1985.1156774","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156774","url":null,"abstract":"A CMOS EEPROM that is fully bipolar PROM compatible at half the power’ and a companion EBPROM, which are metal mask options, will he reported. Both devices have a typical address access of 3511s. Packaged in a 600mil24-pin DIP, the bipolar PROM replacement device, uses a timed 9V signal for progamming. The EPPROM, in a 28-pin DIP, is compatiblc with industry standard 64K latch-timer E2PROMs. The memories use an N-well CblOS process with a single metal layer, two polysilicon layers, 2 p minimum gate lengths and 400a second gate oxides. The process includes N-channel enhancement and depletion transistors as well as P-channel enhancement transistors. Previous attempts to reach the bipolar PROM speeds with EEPROM3 used four transistor cells with differential sensing. The current design uses a conventional two-transistor floating-gate tunnel oxide ell^\"'^ as shown in Figure 2; cutting core area and wordline capacitance in half. The E~PROMS achieve a short access through static NMOS bootstrapping circuit techniques, a single-ended sensing, and substrate bias. Multiple chip enable buffers are used to obtain equal chip enable and address access times. Sixteen columns of redundancy (2 bytes) implemented with EZPROM fuses increase yield. Additionally, data-out circuitry achieves a full 9.6mA 101. Substrate bias generation on P-type non-epitaxial starting material was used to improve performance of N-channel transistors, reduce junction capacitance and eliminate the possibility of latch-up from input and output voltage undershoot. Substrate voltage i s regulated at approximately -2.5V.","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122504168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 1Mb CMOS DRAM with a divided bitline matrix architecture","authors":"R. Taylor, M. Johnson","doi":"10.1109/ISSCC.1985.1156856","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156856","url":null,"abstract":"Application of a divided bitline matrix architecture, combined with a 1.2μ double metal CMOS process has resulted in the development of a 5V 1Mb DRAM with an array area to die ratio of 56.6%. Over 80% of the total die area is repairable using laser programmed redundant rows and columns.","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122167320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Dorman, M. Prisbe, H. Allen, J. Knutti, J. Schott, J. Meindl
{"title":"A monolithic signal processor for neurophysiological telemetry","authors":"M. Dorman, M. Prisbe, H. Allen, J. Knutti, J. Schott, J. Meindl","doi":"10.1109/ISSCC.1985.1156763","DOIUrl":"https://doi.org/10.1109/ISSCC.1985.1156763","url":null,"abstract":"A fully integrated signal processor designed for an eight-channel implantable telemetry system for neurophysiology will be described. Incorporated are integrated bipolar band-pass amplifiers, pulsed thermistor drivers, a multiplexer and I2L logic control that implements a hierarchical multiplexing system and an automatic power down associated with a low bandwidth mode.","PeriodicalId":309244,"journal":{"name":"1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116166703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}