A 20ns static column 1Mb DRAM in CMOS technology

Abstract

RECENT DEMANDS FOR DRAMs involve not only LSI, but high-speed column functions with reduced power consumption. This performance can best be accomplished by CMOS because of its low power dissipation and high-speed characteristics. This paper will report the development of a 1Mb static column DRAM using a back bias generator in N-well CMOS technology, with a column address access time of 20ns, a RAS access time of less than 80ns, and power dissipation of 230mW at 210ns cycle time. A photomicrograph of the chip is shown in Figure 1. The cell size is 3 . 3 5 ~ x 7.2p (=24.12p2) using a Corrugated Capacitor Cell (CCC)’. Die size is 4.68mm x 10.lmm (=47.3mm2) assembled in a 300-mil wide 18-pin DIP; Figure 2. The pin arrangement is also shown in this illustration. In the array memory, a folded-bit-line structure has been used with horizontal metal bit and vertical polycide word lines. The array consists of 16 identical blocks on a P-type substrate, with each block halved by sense amplifiers to reduce bit line capacitance, without increasing the width of the chip. Forming column select signals with a second aluminum layer is also useful in a multi-divided bit line structure’, because no additional column decoders are necessary. The bit line-to-cell capacitance ratio resulting from this multi-divided bit line structure is about 6, producing a total sensing signal of 600mV, with a boosted word line; Figure 3. A half Vcc bit line equalization precharging method* was used for low power consumption of the bit lines. The column circuits, shown in Figure 4, are designed to operate in a high speed static column mode. Therefore, CMOS circuitry is used for static operation. Moreover, the address transition detection (ATD) technique was adopted t o reduce the power dissipation at long cycle times. The ATD clock activates a column driver clock (h), a column select signal (YS), and a main amplifier, for a period of time. The ATD control of YS is demonstrated in Figure 3. Typical measured RAS and static column access times are shown in Figure 5 ; RAS access time is 74ns and static column access time is 20ns at a static column cycle (t/sc) of 20ns. The typical active power dissipa-_