A 15ns 64K bipolar SRAM

Abstract

THIS PAPER WILL DESCRIBE a 64K bipolar SRAM with a cell size of 1 9 0 ~ 2 and 2p features that resulted in an overall die size of 38,608 square mils. Silicided polysilicon has been used to interconnect crosscoupled transistors, polysilicon resistors as load devices, and lateral polysilicon diodes for bit-line coupling devices. Of the six components required for the standard symmetrical static RAM, four are polysilicon. The cross-coupled transistors are collector-up transistors on a buried layer shared by 8 cells. The cell circuit is shown in Figure 1 and the cell layout in Figure 2. Cell operation is outlined in Table 1. Performance of most large memories is limited by the time required to charge and discharge large capacitors associated with word or bit lines. In this cell the longest time delay is in the charging and discharging of the buried layer-substrate capacitor on the selected word line. This delay has been minimized by using divided word lines or squad addressed architecture. The use of squads comprised of 8 cells each results in a 25% increase in array area, but reduces the effective word line capacitance to as little as 2% of its value without squads. The organization of a squad with 8 cells, a resistor and a transistor is shown in Figure 3. The squad driver transistor sinks the high current from the selected squad. The squad resistor recovers the squad to the standby level and sinks the standby current from the squad. The use of silicided polysilicon as the local interconnect within the cell permits three layers of interconnect and allows the use of the divided word line architecture without an area penalty.