An 85ns 1Mb DRAM in a plastic DIP

1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1985.1156852

Y. Inoue, T. Murotani, Y. Fukuzoh, K. Hayano, T. Fujii, K. Minami, K. Nakamura, M. Kikuchi

引用次数: 14

Abstract

This paper will describe the application of an NMOS technology with trench capacitors and an additional polycide interconnect layer to develop a 43.2mm2circuit in a 300mil plastic DIP. A quasi four-bit wide test capability will also be discussed.

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一个85ns 1Mb的塑料DIP内存

本文将描述NMOS技术与沟槽电容器和额外的多晶硅互连层的应用，以在300mil的塑料DIP中开发43.2mm2电路。准4位宽测试能力也将被讨论。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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