Page mode programming 1Mb CMOS EPROM

Abstract

THIS PAPER WILL DESCRIBE a 1Mb CMOS EPROM with fast page mode programming. The EPROM was fabricated using: (I)-high voltage MOS structure with Lightly Doped Drain (LDD), (Z)-double poly N-well CMOS, and (3)-1p minimum gate length for memory transistors. This technology afforded a reduction of cell size to 19.27p2. Thus, it was possible to obtain 1Mb integration in a chip that is 6.0 x 6.56mm2. Scaling down of the memory transistor to a 1p gate length resulted in a wide threshold voltage shift with programming of 11-13V and 0.5ms. Organized as 128K x 8b, the EPROM has both page-mode and conventional byte-mode operation. In page-mode programming, the EPROM accepts four bytes of input data sequentically and programs them at a time; Figure 1. The mode enables programming with time comparable to 256K EPROM’. In this mode, four bytes of input data are stored in 32 latches, and gates of switching transistors on high voltage paths to memory bit lines are controlled by latch outputs when the program enable signal is applied; Figure 2. In a conventional programming mode, the latches are bypassed and the input data controls the switching transistors. A CMOS current sense amplifier with a feedback loop is used; Figure 3. The bit line voltage is lowered (about 1V) to prevent soft writing during read operation. The amplifier has a wide margin for reading operation with a maximum supply voltage of more than TV. Figure 4 shows a microphotograph of the chip. Read access waveforms arc in Figure 5 . Typical access time is 140ns. Power supply current is typically 5mA in active mode and less than IpA in standby mode.