2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)最新文献

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A new charger system approach: The current and voltage control loops 一种新的充电系统方法:电流和电压控制回路
2010 IEEE International Conference on Semiconductor Electronics (ICSE2010) Pub Date : 2010-06-28 DOI: 10.1109/SMELEC.2010.5549350
K. Omar, N. Soin, W. Mahadi, Hassan Malik
{"title":"A new charger system approach: The current and voltage control loops","authors":"K. Omar, N. Soin, W. Mahadi, Hassan Malik","doi":"10.1109/SMELEC.2010.5549350","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549350","url":null,"abstract":"This paper presents a lithium-ion battery recharging circuit with an improved charger system topology for portable devices and handheld gadgets. The proposed charger topology uses an operational amplifier with NMOS input for a smooth transition between current control loop and voltage control loop and to control a power pass element device. Using the above-mentioned abilities, a complete charging process, consisting of three sub-processes; automatically trickle charge, constant current and constant voltage mode are implemented. In the proposed new charger system topology, the charging behaviors of the Li-ion battery can achieve a better charging performance and terminated automatically when fully charged. Simulation results show that the power pass element channel width is 40,000 µm which is less 60% from others design, is able to carry out the output voltage of 4.2 V, the maximum charging current reaches 1 A and the trickle charge is 10% of constant current. The new charger topology has been implemented using 0.18µm CMOS process. Experimental result shows that the new charger design topology agrees with the charging behaviors from simulation results.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123199851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Transparent conducting thin films of fluoro doped tin oxide (FTO) deposited using inkjet printing technique 采用喷墨打印技术制备了含氟氧化锡透明导电薄膜
2010 IEEE International Conference on Semiconductor Electronics (ICSE2010) Pub Date : 2010-06-28 DOI: 10.1109/SMELEC.2010.5549462
Wan Zurina Samad, M. Salleh, A. Shafiee, M. Yarmo
{"title":"Transparent conducting thin films of fluoro doped tin oxide (FTO) deposited using inkjet printing technique","authors":"Wan Zurina Samad, M. Salleh, A. Shafiee, M. Yarmo","doi":"10.1109/SMELEC.2010.5549462","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549462","url":null,"abstract":"FTO thin films were successfully prepared by inkjet printing technique. FTO precursor was prepared by reacting SnCl<inf>4</inf>.5H<inf>2</inf>O and NH<inf>4</inf>F at 60°C in a sealed container. The number of layers was set up from two to five layers on the glass substrate and was deposited at room temperature around 25 to 27° C, 40° C and 60° C to determine the optimum properties for thin films performance. Morphology analysis study using VP-SEM shows the existence of fine grains with the size ranging 20 to 30 nm and the existence of crystal shape with the increases of deposition temperature. Fluorine concentration in the thin films determined from XPS analysis shows the ratio of[F]/[Sn] at 0.02 with the Sn d<inf>5/2</inf> Sn 4+, O<inf>1s</inf> as O<sup>2-</sup>, and F1s as Sn-F bond peaks at binding energy 486.6 eV, 530.5 eV and 684.4 eV. The optical transmittance analysis showed the deposition temperature improved the optical transmittance; 60% T at ambient to 80% T at 60° C. The optimum optical transmittance was 91% T for the thin film deposited at 40° C. The sheet resistances were 16 Ω/□, 21 Ω/□ 23 Ω/□ for the thin film deposited at 40° C, ambient temperature and 60° C.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122554991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Effect of oxide thickness on 32nm Pmosfet reliability 氧化物厚度对32nm Pmosfet可靠性的影响
2010 IEEE International Conference on Semiconductor Electronics (ICSE2010) Pub Date : 2010-06-28 DOI: 10.1109/SMELEC.2010.5549578
D. A. Hadi, S. Hatta, N. Soin
{"title":"Effect of oxide thickness on 32nm Pmosfet reliability","authors":"D. A. Hadi, S. Hatta, N. Soin","doi":"10.1109/SMELEC.2010.5549578","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549578","url":null,"abstract":"Negative Bias Temperature Instability (NBTI) has become one of the critical reliability concerns as scaling down CMOS technology especially on the pMOSFET device. A simulation study had been conducted on 32 nm conventional pMOSFET using the technology CAD (TCAD) Sentaurus Synopsys simulator tool. In this paper, the effects of the gate oxide thickness together with drain bias variations on the NBTI are studied. The effect on the device parameters such as interface traps concentration (Nit), threshold voltage (Vth) and drain current (Id) degradation had been investigated and explained in detail.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"269 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133831274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Wave propagation based analytical delay and cross talk noise model for distributed on-chip RLCG interconnects 基于波传播的分布式片上RLCG互连分析时延和串扰噪声模型
2010 IEEE International Conference on Semiconductor Electronics (ICSE2010) Pub Date : 2010-06-28 DOI: 10.1109/SMELEC.2010.5549381
A. Choudhary, V. Maheshwari, Abhishek Singh, R. Kar
{"title":"Wave propagation based analytical delay and cross talk noise model for distributed on-chip RLCG interconnects","authors":"A. Choudhary, V. Maheshwari, Abhishek Singh, R. Kar","doi":"10.1109/SMELEC.2010.5549381","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549381","url":null,"abstract":"This paper proposes a wave propagation based approach to derive crosstalk and delay between two coupled RLCG interconnects in the transform domain. The increase of clock frequency into the GHz range, coupled with longer length interconnects of small cross-section and low dielectric strength, can result in cross coupling effects between on-chip interconnects. The traditional analysis of crosstalk in a transmission line begins with a lossless LC representation, yielding a wave equation governing the system response. In order to determine the effects that this cross talk will have on circuit operation, the resulting delays and logic levels for the victim nets must be computed. In this paper, we propose four reflection wave propagation based analytical model for estimation of crosstalk. An emphasis was made on the distributed nature of the RLCG model, thus underlining the effect of parasitic coupling inductance and conductance on present and future on-chip interconnects.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124869906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Ubiquitous sensor technologies: The way moving forward 无处不在的传感器技术:前进的道路
2010 IEEE International Conference on Semiconductor Electronics (ICSE2010) Pub Date : 2010-06-28 DOI: 10.1109/SMELEC.2010.5549500
M. Othman
{"title":"Ubiquitous sensor technologies: The way moving forward","authors":"M. Othman","doi":"10.1109/SMELEC.2010.5549500","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549500","url":null,"abstract":"This presentation provides strategic direction for ubiquitous sensor networks and how we can benefit from the technology for the betterment of our lifes. An overview of the global progress is presented and the values of the technology in terms of the realization of WSN implementation in many vertical applications such as in the agriculture, medical, transportation and environment will be given. Some statements of benefits of the technology especially in the areas of medical for human and plants and environmental will be verbalised. Then followed by some case studies especially in the sensor technologies for chemical and bio-sensors will be presented. Issues in the realization both in terms of ethical and technological challenges in bio-medical sensors will be highlighted. MIMOS has been actively pursuing the R&D in bio-chemical sensors especially for the application in the field of agriculture. The multipurpose nature of the design can easily be modified to suit for many other applications in the future. In particular an integrated sensors for monitoring soil and environment (N, P, K, pH, T, Moisture and humidity sensors) has been produced and has been deployed at the POC level in several plantations industries. The R&D findings related to the sensors will be shared during the presentation. Last but not least a systemic approach in conducting and realizing gas sensors for environment will be given. The process established is very important to ensure the deliverables of the sensor systems meeting industrial requirements. A conclusion will be presented at the end of the presentation.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114171295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Correlation study between doping technique towards diffusion rate and oxidation rate 掺杂技术与扩散速率和氧化速率的相关性研究
2010 IEEE International Conference on Semiconductor Electronics (ICSE2010) Pub Date : 2010-06-28 DOI: 10.1109/SMELEC.2010.5549541
A. Zoolfakar, H. Zulkefle, A. Zakaria, A. Manut, Abdul Aziz A, M. Zolkapli
{"title":"Correlation study between doping technique towards diffusion rate and oxidation rate","authors":"A. Zoolfakar, H. Zulkefle, A. Zakaria, A. Manut, Abdul Aziz A, M. Zolkapli","doi":"10.1109/SMELEC.2010.5549541","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549541","url":null,"abstract":"This paper is to investigate correlation between doping technique towards diffusion rate and oxide growth rate. There are two types of doping technique that has been investigated such as Solid Source, SS and Spin on Dopant, SOD. Four inches wafers were used to investigate the effects of doping technique towards diffusion rate and oxidation rate. The resistivity of silicon substrate is measured by using 4-point probe while the oxide thickness is measured by an Ellipsometer. From this experiment, it can be concluded that diffusion rate of Solid Source is about 86% better than Spin on Dopand. While the oxide growth of Solid Source, SS is 3.6% better than Spin on Dopant.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121881366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Amorphous silicon thin-film transistor gate driver circuit design optimization using a simulation-based evolutionary technique 基于模拟进化技术的非晶硅薄膜晶体管栅极驱动电路设计优化
2010 IEEE International Conference on Semiconductor Electronics (ICSE2010) Pub Date : 2010-06-28 DOI: 10.1109/SMELEC.2010.5549386
Ying-Ju Chiu, Kuo-Fu Lee, Ying-Chieh Chen, Hui-Wen Cheng, Yiming Li, Tony Chiang, Kuen-Yu Huang, T. Hsieh
{"title":"Amorphous silicon thin-film transistor gate driver circuit design optimization using a simulation-based evolutionary technique","authors":"Ying-Ju Chiu, Kuo-Fu Lee, Ying-Chieh Chen, Hui-Wen Cheng, Yiming Li, Tony Chiang, Kuen-Yu Huang, T. Hsieh","doi":"10.1109/SMELEC.2010.5549386","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549386","url":null,"abstract":"In this work, we for the first time optimize dynamic characteristic of amorphous silicon thin-film transistor (TFT) gate (ASG) driver circuits for TFT-LCD panel. The rise time, fall time, power dissipation, and ripple voltage of the ASG driver circuit are optimized using simulation-based evolutionary method which integrates genetic algorithm and circuit simulation on the unified optimization framework [1]. Two different a-Si:H TFT ASG driver circuits are optimized, the first circuit consisting of 14 a-Si:H TFT devices is designed for the specification of the rise time < 1.5 µs, the fall time < 1.5 µs and the ripple voltage < 3 V with the minimization of total layout area. The second one with 8 a-Si:H TFTs is further optimized with the power dissipation < 2 mW. The results of this study successfully met the desired specification; consequently, it benefits manufacturing of TFT-LCD panel.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129104559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Optimization of pull-in voltage and contact force for MEMS series switch using Taguchi method 用田口法优化MEMS串联开关的拉入电压和接触力
2010 IEEE International Conference on Semiconductor Electronics (ICSE2010) Pub Date : 2010-06-28 DOI: 10.1109/SMELEC.2010.5549363
Abhijeet Kshirsagar, P. Apte, S. Duttagupta, S. Gangal
{"title":"Optimization of pull-in voltage and contact force for MEMS series switch using Taguchi method","authors":"Abhijeet Kshirsagar, P. Apte, S. Duttagupta, S. Gangal","doi":"10.1109/SMELEC.2010.5549363","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549363","url":null,"abstract":"Cantilever based metal-to-metal contact type MEMS series switch has many applications namely in RFMEMS, Power MEMS etc. A typical MEMS switch consists of a cantilever as actuating element to make the contact between the two metal terminals of the switch. In electrostatic type switches the cantilever is pulled down by applying a pull-in voltage to the control electrode that is located below the middle portion of the cantilever while only the tip portion of the cantilever makes contact between the two terminals. Detailed analysis of bending of the cantilever for different pull-in voltages reveals some interesting facts. At low pull-in voltage the cantilever tip barely touches the two terminals, thus resulting in very less contact area. To increase contact area a very high pull-in voltage is applied. However it lifts the tip from the free end due to concave curving of the cantilever in the middle region of the cantilever where the electrode is located. It again results in less contact area. Furthermore, the high pull-in voltage produces large stress at the base of the cantilever close to the anchor. Therefore, an optimum, pull-in voltage must exist at which the concave curving is eliminated and contact area is maximum. In this paper authors report the procedure for finding a optimum voltage that can give maximum contact force across the two terminals. Taguchi method which is well suited to solve such optimization problem is used in the present work. The switch parameters, like cantilever length, cantilever width, electrode position, thickness of the metal of two terminals, are taken as 'control factors' with 4 levels each and simulation is performed for various combinations of the control factors as these appear in the rows of the L16 orthogonal array. The paper reports the optimum design of the MEMS switch.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129510103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Two-order low-power sigma-delta modulator with SC techniques 基于SC技术的二阶低功耗σ - δ调制器
2010 IEEE International Conference on Semiconductor Electronics (ICSE2010) Pub Date : 2010-06-28 DOI: 10.1109/SMELEC.2010.5549418
Zhang Lei, Zhao Xian-li, Wang Xing-hua, Qu Ruo-yuan
{"title":"Two-order low-power sigma-delta modulator with SC techniques","authors":"Zhang Lei, Zhao Xian-li, Wang Xing-hua, Qu Ruo-yuan","doi":"10.1109/SMELEC.2010.5549418","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549418","url":null,"abstract":"This paper presents a sigma-delta modulator of two-order with switched-capacitors (SC) techniques for low power in 0.18um CMOS process. Without continues current transmission SC techniques present a discrete low power system. And a low power op amplifier with discrete common-mode feedback and a dynamic comparator is also designed. This new amp works under the supply of 1.8v and with the direct current of 200uA. The tool Matlab is used to simulate the behavior system, while Cadence is used to design the circuit and the layout in 0.18 um CMOS (1.8v model) process. The modulator achieves 81dB dynamic range in 24-kHz signal bandwidth with OSR=128. And it consumes 0.8mW under 1.8v supply voltage.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129478382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Analysis of inductive powering harvesting circuit 感应供电采集电路分析
2010 IEEE International Conference on Semiconductor Electronics (ICSE2010) Pub Date : 2010-06-28 DOI: 10.1109/SMELEC.2010.5549378
M. Ya, A. A. Ralib, Nadira Jamil, Sheroz Khan, A. Alam, A. Nurashikin
{"title":"Analysis of inductive powering harvesting circuit","authors":"M. Ya, A. A. Ralib, Nadira Jamil, Sheroz Khan, A. Alam, A. Nurashikin","doi":"10.1109/SMELEC.2010.5549378","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549378","url":null,"abstract":"The use of implanted devices for biomedical applications is on the rise. As reliability and longevity of the power source is an issue of concern so research is underway for using other means of energy sources such as solar, vibrations and inductive coupling, The inductive coupling providing a non-invasive means of energy source, and is hence considered the most reliable contender. In this case the primary coil is wound on an external mount while the secondary (few turns) is embedded on implanted bed. A theoretical and simulation of inductive coupling is done using MATLAB© exploring its frequency response.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123290255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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