2014 15th Latin American Test Workshop - LATW最新文献

The effects of total ionizing dose on the neutron SEU cross section of a 130 nm 4 Mb SRAM memory 总电离剂量对130 nm 4mb SRAM存储器中子SEU截面的影响

2014 15th Latin American Test Workshop - LATW Pub Date : 2014-03-12 DOI: 10.1109/LATW.2014.6841919

E. C. F. Pereira, O. Gonçalez, R. G. Vaz, C. Federico, T. H. Both, G. Wirth

引用次数: 10

Methodology for achieving best trade-off of area and fault masking coverage in ATMR 在ATMR中实现面积和故障掩蔽覆盖率最佳权衡的方法

2014 15th Latin American Test Workshop - LATW Pub Date : 2014-03-12 DOI: 10.1109/LATW.2014.6841916

I. A. C. Gomes, Mayler G. A. Martins, F. Kastensmidt, A. Reis, R. Ribas, Sylvain P. Novales

{"title":"Methodology for achieving best trade-off of area and fault masking coverage in ATMR","authors":"I. A. C. Gomes, Mayler G. A. Martins, F. Kastensmidt, A. Reis, R. Ribas, Sylvain P. Novales","doi":"10.1109/LATW.2014.6841916","DOIUrl":"https://doi.org/10.1109/LATW.2014.6841916","url":null,"abstract":"The use of Triple Modular Redundancy (TMR) with majority voters can guarantee full single fault masking coverage for a given circuit against transient faults. However, it presents a minimum area overhead of 200% compared to the original circuit. In order to reduce area overhead without compromising significantly the fault coverage, TMR can use approximated circuits approach to generate redundant modules that are optimized in area compared to the original module. Initial studies of this technique have shown that it is possible to reach a good balance between fault coverage and area overhead cost. In this work, we do a further analysis of this approach by using a new method to compute approximate functions and to select the best combinations of approximate circuits targeting the highest fault coverage. We use complex gates and employ structural reorder techniques. All the tests are done using a fault injection tool designed specifically for approximate TMR scheme. Results show that area overhead can be reduced greatly from 200% to 120%and still reaching fault coverage of more than 95%.","PeriodicalId":305922,"journal":{"name":"2014 15th Latin American Test Workshop - LATW","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123858951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18

Possibilities of defect-size magnification for testing resistive-opens in nanometer technologies 纳米技术中缺陷尺寸放大测试电阻开口的可能性

2014 15th Latin American Test Workshop - LATW Pub Date : 2014-03-12 DOI: 10.1109/LATW.2014.6841909

J. L. Garcia-Gervacio, J. Martínez-Castillo, V. Champac

{"title":"Possibilities of defect-size magnification for testing resistive-opens in nanometer technologies","authors":"J. L. Garcia-Gervacio, J. Martínez-Castillo, V. Champac","doi":"10.1109/LATW.2014.6841909","DOIUrl":"https://doi.org/10.1109/LATW.2014.6841909","url":null,"abstract":"Small delay defects caused by resistive opens are very common in nanometer technologies due to the rising number of vias and metal levels. The detection of this kind of defects is a major concern in modern circuits. These defects are hard to detect and are an important source of test escapes, and hence they represent a reliability risk. Furthermore, the detection of these defects aggravates in the presence of process variations and gets worse as the technology scales-down. In this paper, a Design-for-Test (DFT) methodology to magnify the defect-size of resistive-open defects is presented. The DFT methodology allows to increase the probability of detection of the defect, and hence the circuit fault coverage. A statistical timing analysis framework (STAF) is used to obtain the timing information of the circuit with and without defect. Process variations, spatial correlation and random dopant fluctuations are considered. Using the timing information given by the STAF, the statistical fault coverage of the circuit is obtained. Simulation results on ISCAS-85 benchmark circuits show promising results of the proposed DFT methodology.","PeriodicalId":305922,"journal":{"name":"2014 15th Latin American Test Workshop - LATW","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114878494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Low cost fault detector guided by permanent faults at the end of FPGAs life cycle 基于fpga生命周期末期永久故障的低成本故障检测器

2014 15th Latin American Test Workshop - LATW Pub Date : 2014-03-12 DOI: 10.1109/LATW.2014.6841912

V. Martins, Frederico Ferlini, D. Lettnin, E. Bezerra

{"title":"Low cost fault detector guided by permanent faults at the end of FPGAs life cycle","authors":"V. Martins, Frederico Ferlini, D. Lettnin, E. Bezerra","doi":"10.1109/LATW.2014.6841912","DOIUrl":"https://doi.org/10.1109/LATW.2014.6841912","url":null,"abstract":"Field Programmable Gate Arrays (FPGAs), as any other electronic devices, are designed according to some life expectancy figures. For this reason, its lifetime is finite given due to appearance of faults caused by the natural physical degradation. In this paper, we present a low cost solution for autonomous detection of faults at the end of FPGAs life cycle. Our proposed methodology starts from a pre-analysis of memory elements belonging to modules under verification. Then, with a proper organization, it is created a list of all memory elements, controlled through a Built-In Self-Test (BIST) implementation via the FPGAs Internal Configuration Access Port (ICAP). By means of this list, a virtual scan chain is created, where the vectors (test and result) are written and read using the FPGA reconfiguration capabilities, which means there is no extra hardware to create the physical scan chain. The detection algorithm is implemented in the available system processing unit. The results show that with a minor increase in the program memory of the digital design, it is possible to perform an offline hardware testing of each sub-module in the existing FPGA, with no need of stopping the remaining of the system.","PeriodicalId":305922,"journal":{"name":"2014 15th Latin American Test Workshop - LATW","volume":"112 15","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131942169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Soft error rate in SRAM-based FPGAs under neutron-induced and TID effects 基于sram的fpga在中子诱导和TID效应下的软错误率

2014 15th Latin American Test Workshop - LATW Pub Date : 2014-03-12 DOI: 10.1109/LATW.2014.6841920

L. Tambara, Jorge Tonfat, R. Reis, F. Kastensmidt, E. C. F. Pereira, R. G. Vaz, O. Gonçalez

引用次数: 6

Analysis of the effects of single event transients on an SAR-ADC based on charge redistribution 基于电荷再分配的单事件瞬态对SAR-ADC的影响分析

2014 15th Latin American Test Workshop - LATW Pub Date : 2014-03-12 DOI: 10.1109/LATW.2014.6841908

A. J. C. Lanot, T. Balen

引用次数: 10

Performance analysis of a clock generator PLL under TID effects 时钟发生器锁相环在TID效应下的性能分析

2014 15th Latin American Test Workshop - LATW Pub Date : 2014-03-12 DOI: 10.1109/LATW.2014.6841921

A. Rossetto, G. Wirth, Ricardo Vanni Dallasen

引用次数: 3

Software-based self-test generation for microprocessors with high-level decision diagrams 具有高层决策图的微处理器基于软件的自检生成

2014 15th Latin American Test Workshop - LATW Pub Date : 2014-03-12 DOI: 10.1109/LATW.2014.6841923

R. Ubar, A. Tsertov, Artjom Jasnetski, M. Brik

引用次数: 13

Development of a digital tool for the simulation of a readout system dedicated for neutrons discrimination 开发了一种数字工具，用于模拟专用于中子鉴别的读出系统

2014 15th Latin American Test Workshop - LATW Pub Date : 2014-03-12 DOI: 10.1109/LATW.2014.6841929

S. Krit, W. Rahajandraibe, K. Castellani-Coulié, G. Micolau, A. Levisse, A. Lyoussi

引用次数: 4

Recent progress of software-related electromagnetic compatibility 软件电磁兼容性的最新进展

2014 15th Latin American Test Workshop - LATW Pub Date : 2014-03-12 DOI: 10.1109/LATW.2014.6841899

Shih-Yi Yuan

引用次数: 1