{"title":"Performance analysis of a clock generator PLL under TID effects","authors":"A. Rossetto, G. Wirth, Ricardo Vanni Dallasen","doi":"10.1109/LATW.2014.6841921","DOIUrl":null,"url":null,"abstract":"Phase-Locked Loops (PLLs) are widely used as frequency synthesizers for clock signal generation. In aerospace environment, however, the performance of the PLL can be degraded due to the radiation exposure, which causes degradation of the parameters of its components. Thereby, this article presents a performance analysis of a clock generator PLL under TID effects. Output frequency, power consumption and control voltage variations are analyzed for different accumulated doses and compared with normal operating results, evidencing the performance degradation. PLL functional failures were also observed and discussed. The circuit was designed in a 0.35μm CMOS process and the simulations were performed using HSPICE simulator.","PeriodicalId":305922,"journal":{"name":"2014 15th Latin American Test Workshop - LATW","volume":"31 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 15th Latin American Test Workshop - LATW","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/LATW.2014.6841921","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
Phase-Locked Loops (PLLs) are widely used as frequency synthesizers for clock signal generation. In aerospace environment, however, the performance of the PLL can be degraded due to the radiation exposure, which causes degradation of the parameters of its components. Thereby, this article presents a performance analysis of a clock generator PLL under TID effects. Output frequency, power consumption and control voltage variations are analyzed for different accumulated doses and compared with normal operating results, evidencing the performance degradation. PLL functional failures were also observed and discussed. The circuit was designed in a 0.35μm CMOS process and the simulations were performed using HSPICE simulator.