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Proceedings of 9th Symposium on Computer Arithmetic最新文献

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Algorithm design for a 30-bit integrated logarithmic processor 30位集成对数处理器的算法设计
Proceedings of 9th Symposium on Computer Arithmetic Pub Date : 1989-09-06 DOI: 10.1109/ARITH.1989.72826
D. Lewis, Lawrence K. Yu
{"title":"Algorithm design for a 30-bit integrated logarithmic processor","authors":"D. Lewis, Lawrence K. Yu","doi":"10.1109/ARITH.1989.72826","DOIUrl":"https://doi.org/10.1109/ARITH.1989.72826","url":null,"abstract":"A description is given of the architecture of an integrated processor that is capable of performing addition and subtraction of 30-b numbers with 20 fractional bits in the logarithmic number system. Previous techniques would require 70 Mb of ROM to implement this processor, which is not feasible for a single-chip implementation. The techniques presented here use a factor of 275 less memory. The key to this is the use of a linear approximation of the nonlinear functions stored in the lookup tables. The functions involved are highly nonlinear in some regions, so variable size regions are used for the approximation. The use of linear approximation alone would still require over 565 kb of ROM. Further compression is obtained by using linear approximation with differential coding of each table. The compression is chosen to minimize ROM size and obtains a further reduction of 55%. A total of 260 kb of ROM is required to implement the processor.<<ETX>>","PeriodicalId":305909,"journal":{"name":"Proceedings of 9th Symposium on Computer Arithmetic","volume":"128 10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120976857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Rounding algorithms for IEEE multipliers IEEE乘法器的舍入算法
Proceedings of 9th Symposium on Computer Arithmetic Pub Date : 1989-09-06 DOI: 10.1109/ARITH.1989.72824
M. Santoro, G. Bewick, M. Horowitz
{"title":"Rounding algorithms for IEEE multipliers","authors":"M. Santoro, G. Bewick, M. Horowitz","doi":"10.1109/ARITH.1989.72824","DOIUrl":"https://doi.org/10.1109/ARITH.1989.72824","url":null,"abstract":"Several technology independent rounding algorithms for multiplying normalized numbers are presented. The first is a simple rounding algorithm suitable for software simulation or moderate performance hardware multipliers. The next two algorithms are parallel addition schemes suitable for high-performance VLSI multipliers. One of them eliminates the carry produced by the lower-order bits from the critical path. Several methods for computing the sticky bit are also presented. Included is a new fast and efficient technique for computing the sticky bit directly from the carry-save form without undergoing the expense of a carry-propagate addition.<<ETX>>","PeriodicalId":305909,"journal":{"name":"Proceedings of 9th Symposium on Computer Arithmetic","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121829240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 87
Optimal group distribution in carry-skip adders 进位跳加器的最优群分布
Proceedings of 9th Symposium on Computer Arithmetic Pub Date : 1989-09-06 DOI: 10.1109/ARITH.1989.72814
S. Turrini
{"title":"Optimal group distribution in carry-skip adders","authors":"S. Turrini","doi":"10.1109/ARITH.1989.72814","DOIUrl":"https://doi.org/10.1109/ARITH.1989.72814","url":null,"abstract":"The carry-skip adder, because of its greater topological regularity and layout simplicity, is considered a good compromise in terms of area and performance. Some general rules have been suggested for its design, but they tend to overlook many important implementation details and cannot be applied to carry-skip adders with more than two levels of carry-skip or with different delays in the carry paths. The result is a nonoptimal distribution of groups and subgroups of the carry-skip circuits, degrading the worst-case delay of the adder. A new algorithm for determining the optimal distribution with no restriction on the number of skip levels is presented. Some results and conclusions are presented regularly in the realization of such an adder in bipolar ECL technology.<<ETX>>","PeriodicalId":305909,"journal":{"name":"Proceedings of 9th Symposium on Computer Arithmetic","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129425127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 95
Optical arithmetic using high-radix symbolic substitution rules 光学算术使用高基数符号替换规则
Proceedings of 9th Symposium on Computer Arithmetic Pub Date : 1989-09-06 DOI: 10.1109/ARITH.1989.72830
K. Hwang, D. Panda
{"title":"Optical arithmetic using high-radix symbolic substitution rules","authors":"K. Hwang, D. Panda","doi":"10.1109/ARITH.1989.72830","DOIUrl":"https://doi.org/10.1109/ARITH.1989.72830","url":null,"abstract":"New optical representations and symbolic substitution (SS) rules are presented for performing high-radix arithmetic in optics. A set of SS rules is proposed for high-radix optical arithmetic, which satisfies the arithmetic completeness property. Tradeoff parameters like representational efficiency, projected speedup, and estimated implementation cost are analyzed. The SS mechanism together with the signed-digit (SD) representation reinforces massive parallelism in optics. A digit-plane architecture, blending very well with the SS technique and SD representation, is considered for implementing high-radix arithmetic. An optical adder, exploiting massive parallelism, is proposed. The set of SS rules and their implementations on a digit-plane architecture provide the basis for achieving pipelining, systolization, and online arithmetic in future optical computers.<<ETX>>","PeriodicalId":305909,"journal":{"name":"Proceedings of 9th Symposium on Computer Arithmetic","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122763393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On a tapered floating point system 在锥形浮点系统上
Proceedings of 9th Symposium on Computer Arithmetic Pub Date : 1989-09-06 DOI: 10.1109/ARITH.1989.72803
Aqil M. Azmi, F. Lombardi
{"title":"On a tapered floating point system","authors":"Aqil M. Azmi, F. Lombardi","doi":"10.1109/ARITH.1989.72803","DOIUrl":"https://doi.org/10.1109/ARITH.1989.72803","url":null,"abstract":"R. Morris (see IEEE Trans. Comput., vol.TC-20, p.1578-9, 1971), suggested adding an extra field to the fixed floating point system, so that exponents can be stored more efficiently. The exponents are stored in the smallest possible space, passing the extra bits to the mantissa. The extra field is used to monitor the current length of the exponent. The gain in precision and/or exponent range outweighs the overhead of the extra field and the processing speed. The authors provide implementation details, error analysis, and some future research ideas. Simulation results are provided for comparison purposes.<<ETX>>","PeriodicalId":305909,"journal":{"name":"Proceedings of 9th Symposium on Computer Arithmetic","volume":"32 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123800164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Design of on-line division unit 联机除法装置的设计
Proceedings of 9th Symposium on Computer Arithmetic Pub Date : 1989-09-06 DOI: 10.1109/ARITH.1989.72808
P. Tu, M. Ercegovac
{"title":"Design of on-line division unit","authors":"P. Tu, M. Ercegovac","doi":"10.1109/ARITH.1989.72808","DOIUrl":"https://doi.org/10.1109/ARITH.1989.72808","url":null,"abstract":"A gate array implementation of a radix-2 floating-point online division algorithm is presented. The design requires 111 equivalent gates per bit and has a cycle time of 24 ns. For 8-b exponent and 24-b mantissa, the design requires 2497 equivalent gates and can fit on an LSI Logic LL9320P chip with a utilization factor 78%.<<ETX>>","PeriodicalId":305909,"journal":{"name":"Proceedings of 9th Symposium on Computer Arithmetic","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116122528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
An accurate, high speed implementation of division by reciprocal approximation 一种精确的、高速的用倒数近似法进行除法的方法
Proceedings of 9th Symposium on Computer Arithmetic Pub Date : 1989-09-06 DOI: 10.1109/ARITH.1989.72810
D. L. Fowler, James E. Smith
{"title":"An accurate, high speed implementation of division by reciprocal approximation","authors":"D. L. Fowler, James E. Smith","doi":"10.1109/ARITH.1989.72810","DOIUrl":"https://doi.org/10.1109/ARITH.1989.72810","url":null,"abstract":"While unlimited accuracy is theoretically possible, it is very important to minimize the number of iteration steps to improve performance and/or to reduce hardware requirements. Consequently, there is an important accuracy/speed/cost tradeoff in reciprocal approximation implementations. A reciprocal approximation implementation is discussed, with special attention given to these tradeoffs. An interpolation method is used to ensure that an initial approximation, held in a ROM table, is as accurate as possible. A method for implementing the iteration steps is given. Special instructions are used so that maximum accuracy can be carried between iteration operations. For 64-b floating-point operands (53-b mantissa), a table lookup and only two iterations are required, and high accuracy is maintained. The rounded reciprocal rarely differs from a true round-to-nearest value based on an infinite precision result. When the results do differ (less than once every 1000 calculations), the difference in accuracy is shown to be less than 0.025 of a least significant bit (LSB).<<ETX>>","PeriodicalId":305909,"journal":{"name":"Proceedings of 9th Symposium on Computer Arithmetic","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134394547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
Some results about on-line computation of functions 关于函数在线计算的一些结果
Proceedings of 9th Symposium on Computer Arithmetic Pub Date : 1989-09-06 DOI: 10.1109/ARITH.1989.72816
J. Duprat, Yvan Herreros, J. Muller
{"title":"Some results about on-line computation of functions","authors":"J. Duprat, Yvan Herreros, J. Muller","doi":"10.1109/ARITH.1989.72816","DOIUrl":"https://doi.org/10.1109/ARITH.1989.72816","url":null,"abstract":"Complexity results that allow the exact determination or bounding of the online delay of most common arithmetic and elementary functions are presented. These results show that many classical online operators presented in the literature are optimal in delay (but not necessarily in period). The authors propose a way to conserve, for large numbers of manipulations, the main advantage of online arithmetic (the capability of digit-level pipelining) by presenting sparse online arithmetic.<<ETX>>","PeriodicalId":305909,"journal":{"name":"Proceedings of 9th Symposium on Computer Arithmetic","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121209058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Radix-4 square root without initial PLA 根号4的平方根，没有初始PLA
Proceedings of 9th Symposium on Computer Arithmetic Pub Date : 1989-09-06 DOI: 10.1109/ARITH.1989.72822
M. Ercegovac, T. Lang
{"title":"Radix-4 square root without initial PLA","authors":"M. Ercegovac, T. Lang","doi":"10.1109/ARITH.1989.72822","DOIUrl":"https://doi.org/10.1109/ARITH.1989.72822","url":null,"abstract":"A systematic derivation of a radix-4 square root algorithm using redundance in the partial residuals and the result is presented. Unlike other similar schemes, the algorithm does not use a table-lookup or programmable logic array (PLA) for the initial step. The scheme can be integrated with division. It also performs on-the-fly conversion and rounding of the result, thus eliminating a carry-propagate step to obtain the final result. The selection function uses 4 b of the result and 8 b of the estimate of the partial residual.<<ETX>>","PeriodicalId":305909,"journal":{"name":"Proceedings of 9th Symposium on Computer Arithmetic","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130680584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 38
Exploiting redundancy in bit-pipelined rational arithmetic 利用位管道有理数算法中的冗余
Proceedings of 9th Symposium on Computer Arithmetic Pub Date : 1989-09-06 DOI: 10.1109/ARITH.1989.72817
Peter Kornerup, D. Matula
{"title":"Exploiting redundancy in bit-pipelined rational arithmetic","authors":"Peter Kornerup, D. Matula","doi":"10.1109/ARITH.1989.72817","DOIUrl":"https://doi.org/10.1109/ARITH.1989.72817","url":null,"abstract":"The authors develop and analyze a redundant continued-fraction representation of the rationals in the implementation of an arithmetic unit for computing the sum, difference, product, quotient, and other useful functions of two rational operands. Their representation of operands and results allows the computations of the unit to be performed in a signed bit-serial, online fashion. Several such units can then be interconnected for the computation of more complicated expressions in a pipelined manner. Redundancy is used to help achieve a small bounded online delay and uniform throughput.<<ETX>>","PeriodicalId":305909,"journal":{"name":"Proceedings of 9th Symposium on Computer Arithmetic","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126854244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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