Design of on-line division unit

Proceedings of 9th Symposium on Computer Arithmetic Pub Date : 1989-09-06 DOI:10.1109/ARITH.1989.72808

P. Tu, M. Ercegovac

引用次数: 12

Abstract

A gate array implementation of a radix-2 floating-point online division algorithm is presented. The design requires 111 equivalent gates per bit and has a cycle time of 24 ns. For 8-b exponent and 24-b mantissa, the design requires 2497 equivalent gates and can fit on an LSI Logic LL9320P chip with a utilization factor 78%.<>

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联机除法装置的设计

提出了一种基于门阵列的基数-2浮点在线除法算法。该设计要求每比特111个等效门，周期时间为24 ns。对于8b指数和24b尾数，该设计需要2497个等效门，可以在利用率为78%的LSI Logic LL9320P芯片上安装

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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