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Proceedings of 9th Symposium on Computer Arithmetic最新文献

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On-line CORDIC algorithms 在线CORDIC算法
Proceedings of 9th Symposium on Computer Arithmetic Pub Date : 1989-09-06 DOI: 10.1109/ARITH.1989.72806
H. Lin, H. Sips
{"title":"On-line CORDIC algorithms","authors":"H. Lin, H. Sips","doi":"10.1109/ARITH.1989.72806","DOIUrl":"https://doi.org/10.1109/ARITH.1989.72806","url":null,"abstract":"The CORDIC algorithms provide a fast way to calculate a number of basic arithmetic functions. A CORDIC calculation takes O(n) steps for a function, where n is the word length of the operands. The speed is limited by the carry propagation in the adders and the I/O throughput. Speed can be improved by introducing redundancy in the calculation circuitry and I/O throughput by doing I/O transfers while calculating. The latter is characteristic for the class of so-called online arithmetic. At the same time, the pin requirements are limited to a single digit per operand. The authors introduce a number of new algorithms that provide an online CORDIC implementation.<<ETX>>","PeriodicalId":305909,"journal":{"name":"Proceedings of 9th Symposium on Computer Arithmetic","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126925999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 62
JANUS, an on-line multiplier/divider for manipulating large numbers 在线乘数/除法器，用于处理大数
Proceedings of 9th Symposium on Computer Arithmetic Pub Date : 1989-09-06 DOI: 10.1109/ARITH.1989.72815
A. Guyot, Yvan Herreros, J. Muller
{"title":"JANUS, an on-line multiplier/divider for manipulating large numbers","authors":"A. Guyot, Yvan Herreros, J. Muller","doi":"10.1109/ARITH.1989.72815","DOIUrl":"https://doi.org/10.1109/ARITH.1989.72815","url":null,"abstract":"The authors deal with the detailed VLSI implementation of a fast bit-serial operator designed to perform very high precision (600 decimal digits) additions, multiplications, and divisions, and some of the applications of the circuit are discussed. Online arithmetic needs carry-free redundant number systems. Frequently, the radix chosen is different from 2, since a carry-free addition algorithm can be used in radix r not=2. In radix 2, carry-free addition is possible, but with two inconveniences: the algorithm seems more complicated, and the delay is larger. The authors show that the first inconvenience vanishes if good binary representation of the digits in radix-2 signed digit notation is chosen.<<ETX>>","PeriodicalId":305909,"journal":{"name":"Proceedings of 9th Symposium on Computer Arithmetic","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126289606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 64
Cascade: hardware for high/variable precision arithmetic 级联:用于高/可变精度算术的硬件
Proceedings of 9th Symposium on Computer Arithmetic Pub Date : 1989-09-06 DOI: 10.1109/ARITH.1989.72825
Tony M. Carter
{"title":"Cascade: hardware for high/variable precision arithmetic","authors":"Tony M. Carter","doi":"10.1109/ARITH.1989.72825","DOIUrl":"https://doi.org/10.1109/ARITH.1989.72825","url":null,"abstract":"The Cascade hardware architecture for high/variable precision arithmetic is described. It uses a radix-16 redundant signed-digit number representation and directly supports single or multiple precision addition, subtraction, multiplication, division, extraction of the square root, and computation of the greatest divisor. It is object-oriented and implements an abstract class of objects, variable precision integers. It provides a complete suite of memory management functions implemented in hardware, including a garbage collector. The Cascade hardware permits free tradeoffs of space versus time.<<ETX>>","PeriodicalId":305909,"journal":{"name":"Proceedings of 9th Symposium on Computer Arithmetic","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133872174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Design of an on-line multiply-add module for recursive digital filters 递归数字滤波器在线乘加模块的设计
Proceedings of 9th Symposium on Computer Arithmetic Pub Date : 1989-09-06 DOI: 10.1109/ARITH.1989.72807
R. H. Brackert, M. Ercegovac, A. Willson
{"title":"Design of an on-line multiply-add module for recursive digital filters","authors":"R. H. Brackert, M. Ercegovac, A. Willson","doi":"10.1109/ARITH.1989.72807","DOIUrl":"https://doi.org/10.1109/ARITH.1989.72807","url":null,"abstract":"An online multiply-add module that allows high filter sampling rates when used to implement the direct form II second-order filter structure is described. Important characteristics of online arithmetic are that it produces most significant digit first and that its digit cycle time is independent of the data wordlength. These features not only permit high-speed filtering, but also allow the elimination of all nonlinear oscillation in the filter without affecting the sampling rate, and effectively eliminate scaling of the filter's input data. The derivation of the online multiply-add algorithm and its hardware design using a 1.5- mu m CMOS standard cell library are presented. A method for eliminating nonlinear oscillations by increasing the filter's working precision is described.<<ETX>>","PeriodicalId":305909,"journal":{"name":"Proceedings of 9th Symposium on Computer Arithmetic","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117259823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Redundant logarithmic number systems 冗余对数数制
Proceedings of 9th Symposium on Computer Arithmetic Pub Date : 1989-09-06 DOI: 10.1109/ARITH.1989.72820
M. Arnold, T. Bailey, J. Cowles, J. Cupal
{"title":"Redundant logarithmic number systems","authors":"M. Arnold, T. Bailey, J. Cowles, J. Cupal","doi":"10.1109/ARITH.1989.72820","DOIUrl":"https://doi.org/10.1109/ARITH.1989.72820","url":null,"abstract":"A new number system that offers advantages over conventional floating-point and sign/logarithm number systems is described. Called redundant logarithmic arithmetic, it relies, like conventional logarithmic arithmetic, on table lookups to make the arithmetic unit simpler than an equivalent floating-point unit. The cost of 32-b subtraction in a redundant logarithmic number system is lower than that of previously published logarithmic subtraction methods. Another advantage of a redundant logarithmic number system is that a single arithmetic unit can use the same hardware to add, subtract, or multiply in similar times.<<ETX>>","PeriodicalId":305909,"journal":{"name":"Proceedings of 9th Symposium on Computer Arithmetic","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128418160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Concurrent error detection in arithmetic and logical operations using Berger codes 用伯杰码并发检测算术和逻辑运算中的错误
Proceedings of 9th Symposium on Computer Arithmetic Pub Date : 1989-09-06 DOI: 10.1109/ARITH.1989.72831
Jien-Chung Lo, S. Thanawastien, T. Rao
{"title":"Concurrent error detection in arithmetic and logical operations using Berger codes","authors":"Jien-Chung Lo, S. Thanawastien, T. Rao","doi":"10.1109/ARITH.1989.72831","DOIUrl":"https://doi.org/10.1109/ARITH.1989.72831","url":null,"abstract":"A novel approach to designing concurrent-error-detecting arithmetic and logic units using Berger code is presented. Several theorems are developed on Berger check predictions for arithmetic and logical operations. Specifically, the Berger check prediction is proposed for additions and subtractions with unsigned numbers as well as signed numbers. Berger check prediction for 16 logical operations and shift operations, multiplication, and division are given. The proposed scheme may provide a considerable saving in the hardware logic (or chip area) in implementing a self-checking arithmetic logic unit (ALU) and may ultimately make feasible a single-chip self-checking microprocessor or reduced-instruction-set-computer (RISC) design.<<ETX>>","PeriodicalId":305909,"journal":{"name":"Proceedings of 9th Symposium on Computer Arithmetic","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132158876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 40
On-the-fly rounding for division and square root 除法和平方根的动态舍入
Proceedings of 9th Symposium on Computer Arithmetic Pub Date : 1989-09-06 DOI: 10.1109/ARITH.1989.72823
M. Ercegovac, T. Lang
{"title":"On-the-fly rounding for division and square root","authors":"M. Ercegovac, T. Lang","doi":"10.1109/ARITH.1989.72823","DOIUrl":"https://doi.org/10.1109/ARITH.1989.72823","url":null,"abstract":"In division and square root implementation based on digit-recurrence algorithms, the result is obtained in digit-serial form, from most significant digit to least significant. To reduce the complexity of the result-digit selection and to allow the use of redundant addition, the result-digit has values from a signed-digit set. As a consequence, the result has to be converted to conventional representation. This conversion can be done on-the-fly as the digits are produced, without the use of a carry-propagate adder. The authors describe how to modify this conversion process so that the result is rounded. The resulting operation is faster than what is done conventionally because no carry-propagate addition is needed. Three rounding methods that differ in the rounding error and the hardware and time required are described.<<ETX>>","PeriodicalId":305909,"journal":{"name":"Proceedings of 9th Symposium on Computer Arithmetic","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123557721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Implementing infinite precision arithmetic 实现无限精度算法
Proceedings of 9th Symposium on Computer Arithmetic Pub Date : 1989-09-06 DOI: 10.1109/ARITH.1989.72804
J. Schwarz
{"title":"Implementing infinite precision arithmetic","authors":"J. Schwarz","doi":"10.1109/ARITH.1989.72804","DOIUrl":"https://doi.org/10.1109/ARITH.1989.72804","url":null,"abstract":"A data structure for exact representation of real numbers is presented. The representation allows exact computation involving ordinary arithmetic operations on rationals, irrationals, and even some transcendental values (such as pi ). Functions defined by infinite series can also be exactly evaluated. Algorithms are described and analyzed. An implementation in C++ is described.<<ETX>>","PeriodicalId":305909,"journal":{"name":"Proceedings of 9th Symposium on Computer Arithmetic","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125555898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Polyphase convolvers 多相卷积器
Proceedings of 9th Symposium on Computer Arithmetic Pub Date : 1900-01-01 DOI: 10.1109/ARITH.1989.72812
L. Dadda
{"title":"Polyphase convolvers","authors":"L. Dadda","doi":"10.1109/ARITH.1989.72812","DOIUrl":"https://doi.org/10.1109/ARITH.1989.72812","url":null,"abstract":"A general theory of serial-input-serial-output polyphase convolvers based on modules (phases) producing one convolved output every p samples is presented. Methods are presented for designing these convolvers for arbitrarily assigned weights, sample lengths, and number of convolution terms, under the assumption of zero, or assigned, interval between successive samples, minimum number of phases, and minimum intervals between successive convolved output from each phase. Two types of solution are shown, the first based on the use of distinct serial-parallel multipliers and the second on multipliers partially shared among successive convolution terms. A structure based on bit-slices is presented, permitting a convolver with assigned parameters to be designed from a stack of slices.<<ETX>>","PeriodicalId":305909,"journal":{"name":"Proceedings of 9th Symposium on Computer Arithmetic","volume":"77 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114085508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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