{"title":"递归数字滤波器在线乘加模块的设计","authors":"R. H. Brackert, M. Ercegovac, A. Willson","doi":"10.1109/ARITH.1989.72807","DOIUrl":null,"url":null,"abstract":"An online multiply-add module that allows high filter sampling rates when used to implement the direct form II second-order filter structure is described. Important characteristics of online arithmetic are that it produces most significant digit first and that its digit cycle time is independent of the data wordlength. These features not only permit high-speed filtering, but also allow the elimination of all nonlinear oscillation in the filter without affecting the sampling rate, and effectively eliminate scaling of the filter's input data. The derivation of the online multiply-add algorithm and its hardware design using a 1.5- mu m CMOS standard cell library are presented. A method for eliminating nonlinear oscillations by increasing the filter's working precision is described.<<ETX>>","PeriodicalId":305909,"journal":{"name":"Proceedings of 9th Symposium on Computer Arithmetic","volume":"32 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"25","resultStr":"{\"title\":\"Design of an on-line multiply-add module for recursive digital filters\",\"authors\":\"R. H. Brackert, M. Ercegovac, A. Willson\",\"doi\":\"10.1109/ARITH.1989.72807\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An online multiply-add module that allows high filter sampling rates when used to implement the direct form II second-order filter structure is described. Important characteristics of online arithmetic are that it produces most significant digit first and that its digit cycle time is independent of the data wordlength. These features not only permit high-speed filtering, but also allow the elimination of all nonlinear oscillation in the filter without affecting the sampling rate, and effectively eliminate scaling of the filter's input data. The derivation of the online multiply-add algorithm and its hardware design using a 1.5- mu m CMOS standard cell library are presented. A method for eliminating nonlinear oscillations by increasing the filter's working precision is described.<<ETX>>\",\"PeriodicalId\":305909,\"journal\":{\"name\":\"Proceedings of 9th Symposium on Computer Arithmetic\",\"volume\":\"32 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-09-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"25\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 9th Symposium on Computer Arithmetic\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ARITH.1989.72807\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 9th Symposium on Computer Arithmetic","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ARITH.1989.72807","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 25
摘要
描述了一种在线乘加模块,当用于实现直接形式II二阶滤波器结构时,该模块允许高滤波器采样率。在线算法的重要特点是它首先产生最高有效数字,并且它的数字周期时间与数据字长无关。这些特性不仅允许高速滤波,还允许在不影响采样率的情况下消除滤波器中的所有非线性振荡,并有效消除滤波器输入数据的缩放。给出了基于1.5 μ m CMOS标准单元库的在线乘加算法的推导和硬件设计。本文描述了一种通过提高滤波器的工作精度来消除非线性振荡的方法
Design of an on-line multiply-add module for recursive digital filters
An online multiply-add module that allows high filter sampling rates when used to implement the direct form II second-order filter structure is described. Important characteristics of online arithmetic are that it produces most significant digit first and that its digit cycle time is independent of the data wordlength. These features not only permit high-speed filtering, but also allow the elimination of all nonlinear oscillation in the filter without affecting the sampling rate, and effectively eliminate scaling of the filter's input data. The derivation of the online multiply-add algorithm and its hardware design using a 1.5- mu m CMOS standard cell library are presented. A method for eliminating nonlinear oscillations by increasing the filter's working precision is described.<>