Rounding algorithms for IEEE multipliers

Abstract

Several technology independent rounding algorithms for multiplying normalized numbers are presented. The first is a simple rounding algorithm suitable for software simulation or moderate performance hardware multipliers. The next two algorithms are parallel addition schemes suitable for high-performance VLSI multipliers. One of them eliminates the carry produced by the lower-order bits from the critical path. Several methods for computing the sticky bit are also presented. Included is a new fast and efficient technique for computing the sticky bit directly from the carry-save form without undergoing the expense of a carry-propagate addition.<>