2007 Design, Automation & Test in Europe Conference & Exhibition最新文献_第6页

Re-Configuration of Sub-blocks for Effective Application of Time Domain Tests 有效应用时域测试的子块重构

2007 Design, Automation & Test in Europe Conference & Exhibition Pub Date : 2007-04-16 DOI: 10.1109/DATE.2007.364678

J. Anders, Shaji Krishnan, G. Gronthoud

引用次数: 0

Trade-Off Design of Analog Circuits using Goal Attainment and "Wave Front" Sequential Quadratic Programming 基于目标实现和“波前”顺序二次规划的模拟电路权衡设计

2007 Design, Automation & Test in Europe Conference & Exhibition Pub Date : 2007-04-16 DOI: 10.1109/DATE.2007.364570

D. Mueller, H. Graeb, Ulf Schlichtmann

引用次数: 26

A Framework for System Reliability Analysis Considering Both System Error Tolerance and Component Test Quality 考虑系统容错和组件测试质量的系统可靠性分析框架

2007 Design, Automation & Test in Europe Conference & Exhibition Pub Date : 2007-04-16 DOI: 10.1145/1266366.1266714

Sung-Jui Pan, K. Cheng

{"title":"A Framework for System Reliability Analysis Considering Both System Error Tolerance and Component Test Quality","authors":"Sung-Jui Pan, K. Cheng","doi":"10.1145/1266366.1266714","DOIUrl":"https://doi.org/10.1145/1266366.1266714","url":null,"abstract":"The failure rate, the sources of failures and the test costs for nanometer devices are all increasing. Therefore, to create a reliable system-on-a-chip device requires designers to implement fault tolerance. However, while system-level fault tolerance could significantly relax the quality requirements of the system's building blocks, every fault-tolerant scheme only works under certain failure mechanisms and within a certain range of error probabilities. Also, designing a system with a high failure-rate component could be very expensive because the growth rate of the design complexity and the system overhead for fault tolerance could be significantly greater than the component failure rate. Therefore, it is desirable to understand the trade-offs between component test quality and system fault-tolerant capability for achieving the desired reliability under cost constraints. In this paper, the authors propose an analysis framework for system reliability considering (a) the test quality achieved by manufacturing testing, on-line self-checking, and off-line built-in self-test; (b) the fault-tolerant and spare schemes; and (c) the component defect and error probabilities. The authors demonstrate that, through proper redundancy configurations and low-cost testing to insure a certain degree of component test quality, a low-redundant system might achieve equal or higher reliability than a high-redundant system","PeriodicalId":298961,"journal":{"name":"2007 Design, Automation & Test in Europe Conference & Exhibition","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114444886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 19

A New Technique for Characterization of Digital-to-Analog Converters in High-Speed Systems 高速系统数模转换器特性的新技术

2007 Design, Automation & Test in Europe Conference & Exhibition Pub Date : 2007-04-16 DOI: 10.1109/DATE.2007.364630

J. Savoj, A. Abbasfar, A. Amirkhany, B. Garlepp, M. Horowitz

引用次数: 20

Generating and Executing Multi-Exit Custom Instructions for an Adaptive Extensible Processor 自适应可扩展处理器的多出口自定义指令的生成和执行

2007 Design, Automation & Test in Europe Conference & Exhibition Pub Date : 2007-04-16 DOI: 10.1109/DATE.2007.364612

Hamid Noori, Farhad Mehdipour, K. Murakami, Koji Inoue, M. Goudarzi

引用次数: 6

Double-Via-Driven Standard Cell Library Design 双孔驱动标准细胞库设计

2007 Design, Automation & Test in Europe Conference & Exhibition Pub Date : 2007-04-16 DOI: 10.1145/1266366.1266627

Tsai-Ying Lin, Tsung-Han Lin, Hui-Hsiang Tung, Rung-Bin Lin

引用次数: 12

Automatic Synthesis of Compressor Trees: Reevaluating Large Counters 压缩树的自动合成:重新评估大型计数器

2007 Design, Automation & Test in Europe Conference & Exhibition Pub Date : 2007-04-16 DOI: 10.1109/DATE.2007.364632

A. K. Verma, P. Ienne

{"title":"Automatic Synthesis of Compressor Trees: Reevaluating Large Counters","authors":"A. K. Verma, P. Ienne","doi":"10.1109/DATE.2007.364632","DOIUrl":"https://doi.org/10.1109/DATE.2007.364632","url":null,"abstract":"Despite the progress of the last decades in electronic design automation, arithmetic circuits have always received way less attention than other classes of digital circuits. Logic synthesisers, which play a fundamental role in design today, play a minor role on most arithmetic circuits, performing some local optimisations but hardly improving the overall structure of arithmetic components. Architectural optimisations have been often studied manually, and only in the case of very common building blocks such as fast adders and multi-input adders, ad-hoc techniques have been developed. A notable case is multi-input addition, which is the core of many circuits such as multipliers, etc. The most common technique to implement multi-input addition is using compressor trees, which are often composed of carry-save adders (based on (3 : 2) counters, i.e., full adders). A large body of literature exists to implement compressor trees using large counters. However, all the large counters were built by using full and half adders recursively. In this paper we give some definite answers to issues related to the use of large counters. We present a general technique to implement large counters whose performance is much better than the ones composed of full and half adders. Also we show that it is not always useful to use larger optimised counters and sometimes a combination of various size counters gives the best performance. Our results show 15% improvement in the critical path delay. In some cases even hardware area is reduced by using our counters","PeriodicalId":298961,"journal":{"name":"2007 Design, Automation & Test in Europe Conference & Exhibition","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121614435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 28

A Tiny and Efficient Wireless Ad-hoc Protocol for Low-cost Sensor Networks 一种用于低成本传感器网络的小型高效无线自组织协议

2007 Design, Automation & Test in Europe Conference & Exhibition Pub Date : 2007-04-16 DOI: 10.1145/1266366.1266709

P. Gburzynski, B. Kaminska, W. Olesinski

引用次数: 22

An FPGA Based All-Digital Transmitter with Radio Frequency Output for Software Defined Radio 基于FPGA的软件无线电全数字射频输出发射机

2007 Design, Automation & Test in Europe Conference & Exhibition Pub Date : 2007-04-16 DOI: 10.1109/DATE.2007.364561

Zhuan Ye, J. Grosspietsch, G. Memik

{"title":"An FPGA Based All-Digital Transmitter with Radio Frequency Output for Software Defined Radio","authors":"Zhuan Ye, J. Grosspietsch, G. Memik","doi":"10.1109/DATE.2007.364561","DOIUrl":"https://doi.org/10.1109/DATE.2007.364561","url":null,"abstract":"This paper presents the architecture and implementation of an all-digital transmitter with radio frequency output targeting an FPGA device. FPGA devices have been widely adopted in the applications of digital signal processing (DSP) and digital communication. They are typically well suited for the evolving technology of software defined radios (SDR) due to their reconfigurability and programmability. However, FPGA devices are mostly used to implement digital baseband and intermediate frequency (IF) functionalities. Therefore, significant analog and RF components are still needed to fulfill the radio communication requirements. The all-digital transmitter presented in this paper directly synthesizes RF signal in the digital domain, therefore eliminates the need for most of the analog and RF components. The all-digital transmitter consists of one QAM modulator and one RF pulse width modulator (RFPWM). The binary output waveform from RFPWM is centered at 800MHz with 64QAM signaling format. The entire transmitter is implemented using Xilinx Virtex2pro device with on chip multi-gigabit transceiver (MGT). The adjacent channel leakage ratio (ACLR) measured in the 20 MHz passband is 45dB, and the measured error vector magnitude (EVM) is less than 1%. Our work extends the digital implementation of communication applications on an FPGA platform to radio frequency, therefore making a significant evolution towards an ideal SDR","PeriodicalId":298961,"journal":{"name":"2007 Design, Automation & Test in Europe Conference & Exhibition","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124305213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 43

Boosting the Role of Inductive Invariants in Model Checking 增强归纳不变量在模型检验中的作用

2007 Design, Automation & Test in Europe Conference & Exhibition Pub Date : 2007-04-16 DOI: 10.1145/1266366.1266654

G. Cabodi, Sergio Nocco, S. Quer

引用次数: 6