2007 Design, Automation & Test in Europe Conference & Exhibition最新文献_第10页

An Efficient Hardware Architecture for H.264 Intra Prediction Algorithm H.264帧内预测算法的高效硬件架构

2007 Design, Automation & Test in Europe Conference & Exhibition Pub Date : 2007-04-16 DOI: 10.1109/DATE.2007.364588

E. Sahin, Ilker Hamzaoglu

引用次数: 38

Executable system-level specification models containing UML-based behavioral patterns 包含基于uml的行为模式的可执行系统级规范模型

2007 Design, Automation & Test in Europe Conference & Exhibition Pub Date : 2007-04-16 DOI: 10.1109/DATE.2007.364608

L. Indrusiak, A. Thuy, M. Glesner

引用次数: 12

Working with Process Variation Aware Caches 使用过程变化感知缓存

2007 Design, Automation & Test in Europe Conference & Exhibition Pub Date : 2007-04-16 DOI: 10.1145/1266366.1266615

M. Mutyam, N. Vijaykrishnan

{"title":"Working with Process Variation Aware Caches","authors":"M. Mutyam, N. Vijaykrishnan","doi":"10.1145/1266366.1266615","DOIUrl":"https://doi.org/10.1145/1266366.1266615","url":null,"abstract":"Deep-submicron designs have to take care of process variation effects as variations in critical process parameters result in large variations in access latencies of hardware components. This is severe in the case of memory components as minimum sized transistors are used in their design. In this work, by considering on-chip data caches, we study the effect of access latency variations on performance. We discuss performance losses due to the worst-case design, wherein the entire cache operates with the worst-case process variation delay, followed by process variation aware cache designs which work at set-level granularity. We then propose a technique called block rearrangement to minimize performance loss incurred by a process variation aware cache which works at set-level granularity. Using block rearrangement technique, we rearrange the physical locations of cache blocks such that a cache set can have its \"n\" blocks (assuming a n-way set-associative cache) in multiple rows instead of a single row as in the case of a cache with conventional addressing scheme. By distributing blocks of a cache set over multiple sets, we minimize the number of sets being affected by process variation. We evaluate our technique using SPEC2000 CPU benchmarks and show that our technique achieves significant performance benefits over caches with conventional addressing scheme","PeriodicalId":298961,"journal":{"name":"2007 Design, Automation & Test in Europe Conference & Exhibition","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131899147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 33

Temperature-aware NBTI modeling and the impact of input vector control on performance degradation 温度感知的NBTI建模及输入矢量控制对性能退化的影响

2007 Design, Automation & Test in Europe Conference & Exhibition Pub Date : 2007-04-16 DOI: 10.1109/DATE.2007.364650

Yu Wang, Hong Luo, Ku He, Rong Luo, Huazhong Yang, Yuan Xie

{"title":"Temperature-aware NBTI modeling and the impact of input vector control on performance degradation","authors":"Yu Wang, Hong Luo, Ku He, Rong Luo, Huazhong Yang, Yuan Xie","doi":"10.1109/DATE.2007.364650","DOIUrl":"https://doi.org/10.1109/DATE.2007.364650","url":null,"abstract":"As technology scales, negative bias temperature instability (NBTI), which causes temporal performance degradation in digital circuits by affecting PMOS threshold voltage, is emerging as one of the major circuit reliability concerns. In this paper, the authors first investigate the impact of NBTI on PMOS devices and propose a novel temporal performance degradation model for digital circuits considering the temperature difference between active and standby mode. For the first time, the impact of input vector control (to minimize standby leakage) on the NBTI is investigated. Minimum leakage vectors, which lead to minimum circuit performance degradation and remains maximum leakage reduction rate, are selected and used during the standby mode. Furthermore, the potential to save the circuit performance degradation by internal node control techniques during circuit standby mode is discussed. Our simulation results show that: 1) the active and standby time ratio and the standby mode temperature have considerable impact on the circuit performance degradation; 2) the NBTI-aware IVC technique leads to an average 3% savings of the total circuit degradation; while the potential of internal node control may lead to 10% savings of the total circuit degradation","PeriodicalId":298961,"journal":{"name":"2007 Design, Automation & Test in Europe Conference & Exhibition","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130571687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 90

Pulse propagation for the detection of small delay defects 小延迟缺陷的脉冲传播检测

2007 Design, Automation & Test in Europe Conference & Exhibition Pub Date : 2007-04-16 DOI: 10.1145/1266366.1266649

M. Favalli, C. Metra

引用次数: 5

Register Pointer Architecture for Efficient Embedded Processors 高效嵌入式处理器的寄存器指针体系结构

2007 Design, Automation & Test in Europe Conference & Exhibition Pub Date : 2007-04-16 DOI: 10.1109/DATE.2007.364659

Jongsoo Park, Sung-Boem Park, J. Balfour, D. Black-Schaffer, C. Kozyrakis, W. Dally

{"title":"Register Pointer Architecture for Efficient Embedded Processors","authors":"Jongsoo Park, Sung-Boem Park, J. Balfour, D. Black-Schaffer, C. Kozyrakis, W. Dally","doi":"10.1109/DATE.2007.364659","DOIUrl":"https://doi.org/10.1109/DATE.2007.364659","url":null,"abstract":"Conventional register file architectures cannot optimally exploit temporal locality in data references due to their limited capacity and static encoding of register addresses in instructions. In conventional embedded architectures, the register file capacity cannot be increased without resorting to longer instruction words. Similarly, loop unrolling is often required to exploit locality in the register file accesses across iterations because naming registers statically is inflexible. Both optimizations lead to significant code size increases, which is undesirable in embedded systems. In this paper, the authors introduce the register pointer architecture (RPA), which allows registers to be accessed indirectly through register pointers. Indirection allows a larger register file to be used without increasing the length of instruction words. Additional register file capacity allows many loads and stores, such as those introduced by spill code, to be eliminated, which improves performance and reduces energy consumption. Moreover, indirection affords additional flexibility in naming registers, which reduces the need to apply loop unrolling in order to maximize reuse of register allocated variables","PeriodicalId":298961,"journal":{"name":"2007 Design, Automation & Test in Europe Conference & Exhibition","volume":"500 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120933205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

Incremental ABV for Functional Validation of TL-to-RTL Design Refinement 增量ABV用于从tl到rtl设计细化的功能验证

2007 Design, Automation & Test in Europe Conference & Exhibition Pub Date : 2007-04-16 DOI: 10.5555/1266366.1266557

N. Bombieri, F. Fummi, G. Pravadelli

引用次数: 29

Experimental Validation of a Tuning Algorithm for High-Speed Filters 一种高速滤波器调谐算法的实验验证

2007 Design, Automation & Test in Europe Conference & Exhibition Pub Date : 2007-04-16 DOI: 10.1109/DATE.2007.364628

G. Matarrese, C. Marzocca, F. Corsi, S. D’Amico, A. Baschirotto

{"title":"Experimental Validation of a Tuning Algorithm for High-Speed Filters","authors":"G. Matarrese, C. Marzocca, F. Corsi, S. D’Amico, A. Baschirotto","doi":"10.1109/DATE.2007.364628","DOIUrl":"https://doi.org/10.1109/DATE.2007.364628","url":null,"abstract":"We report here the results of some laboratory experiments performed to validate the effectiveness of a technique for the self tuning of integrated continuous-time, high-speed active filters. The tuning algorithm is based on the application of a pseudo-random input sequence of rectangular pulses to the device to be tuned and on the evaluation of a few samples of the input-output cross-correlation function which constitute the filter signature. The key advantages of this technique are the ease of the input test pattern generation and the simplicity of the output circuitry which consists of a digital cross-correlator. The technique allows achieving a tuning error mainly dominated by the value of the elementary capacitors employed in the tuning circuitry. The time required to perform the tuning is kept within a few microseconds. This appears particularly interesting for applications to telecommunication multi-standard terminals. The experiments regarding the application of the proposed tuning algorithm to a baseband multi-standard filter confirm most of the simulation results and show the robustness of the technique against practical operating conditions and noise","PeriodicalId":298961,"journal":{"name":"2007 Design, Automation & Test in Europe Conference & Exhibition","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131224085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A One-Shot Configurable-Cache Tuner for Improved Energy and Performance 一次性配置缓存调谐器，提高能源和性能

2007 Design, Automation & Test in Europe Conference & Exhibition Pub Date : 2007-04-16 DOI: 10.1109/DATE.2007.364686

A. Gordon-Ross, Pablo Viana, F. Vahid, W. Najjar, E. Barros

{"title":"A One-Shot Configurable-Cache Tuner for Improved Energy and Performance","authors":"A. Gordon-Ross, Pablo Viana, F. Vahid, W. Najjar, E. Barros","doi":"10.1109/DATE.2007.364686","DOIUrl":"https://doi.org/10.1109/DATE.2007.364686","url":null,"abstract":"We introduce a new non-intrusive on-chip cache-tuning hardware module capable of accurately predicting the best configuration of a configurable cache for an executing application. Previous dynamic cache tuning approaches change the cache configuration several times as part of the tuning search process, executing the application using inferior configurations and temporarily causing energy and performance overhead. The introduced tuner uses a different approach, which non-intrusively collects data on addresses issued by the microprocessor, analyzes that data to predict the best cache configuration, and then updates the cache to the new best configuration in \"one-shot\", without ever having to examine inferior configurations. The result is less energy and less performance overhead, meaning that cache tuning can be applied more frequently. We show through experiments that the one-shot cache tuner can reduce memory-access related energy for instructions by 35% and comes within 4% of a previous intrusive approach, and results in 4.6 times less energy overhead and a 7.7 times speedup in tuning time compared to a previous intrusive approach, at the main expense of 12% larger size","PeriodicalId":298961,"journal":{"name":"2007 Design, Automation & Test in Europe Conference & Exhibition","volume":"208 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132816656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 34

Low Power Design on Algorithmic and Architectural Level: A Case Study of an HSDPA Baseband Digital Signal Processing System 基于算法和体系结构的低功耗设计——以HSDPA基带数字信号处理系统为例

2007 Design, Automation & Test in Europe Conference & Exhibition Pub Date : 2007-04-16 DOI: 10.1109/DATE.2007.364495

Marcus Schämann, S. Hessel, U. Langmann, Martin Bücker

引用次数: 1