2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems最新文献

Evaluation of the Iddq Signature in devices with Gauss-distributed background current 具有高斯分布背景电流的器件Iddq签名的评估

2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2008-04-16 DOI: 10.1109/DDECS.2008.4538793

J. Schat

{"title":"Evaluation of the Iddq Signature in devices with Gauss-distributed background current","authors":"J. Schat","doi":"10.1109/DDECS.2008.4538793","DOIUrl":"https://doi.org/10.1109/DDECS.2008.4538793","url":null,"abstract":"In the last decade, the single-threshold IDDQ approach made way for more elaborated techniques like Delta-IDDQ and adaptive IDDQ. Due to increasing background currents, however, also these methods are beginning to have problems to distinguish between good and bad devices. A good evaluation algorithm for IDDQ takes all known information about 'good' and 'bad' parts into account, i.e. it 'knows' how the IDDQ signatures of good and bad parts look like. Unfortunately, not only do the signatures of good parts differ significantly, but the signatures of bad parts differ even more. Moreover, since IDDQ faults are more often than not non-fatal (not impairing the functionality), it is frequently hard to say if a device is really 'good' or bad'. There are two kinds of information, however, which are known without referring to a certain process or IC type: one is the model of the IDDQ fault, and the other is the statistical distribution of the background-IDDQ. Using this information, an estimator with higher discrimination capability than the traditional Delta-IDDQ-approach is created. Measurement results form several lots of a 180 nm chip are presented..","PeriodicalId":297689,"journal":{"name":"2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117276868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Improving Fault Tolerance by Using Reconfigurable Asynchronous Circuits 利用可重构异步电路提高容错性

2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2008-04-16 DOI: 10.1109/DDECS.2008.4538799

W. Friesenbichler, T. Panhofer, M. Delvai

{"title":"Improving Fault Tolerance by Using Reconfigurable Asynchronous Circuits","authors":"W. Friesenbichler, T. Panhofer, M. Delvai","doi":"10.1109/DDECS.2008.4538799","DOIUrl":"https://doi.org/10.1109/DDECS.2008.4538799","url":null,"abstract":"To achieve fault tolerance several tasks have to be performed, from fault detection up to recovery procedures. Sophisticated methods for each sub-task were and are still developed, but rarely a complete solution is proposed on circuit level. This paper fills the gap by proposing a concept that combines all required steps to implement fault tolerant digital circuits. The approach is based on asynchronous Four-State Logic (FSL) logic, which belongs to the family of Quasi Delay Insensitive (QDI) circuits. Contrary to conventional approaches, using synchronous logic plus additional hardware and/or software to achieve fault tolerance, we use the inherent properties of FSL for fault detection, fault localization and fault recovery. Only deadlock detection and error mitigation require an enhancement of the conventional FSL (four state logic) design. For this purpose, a monitoring unit has to be added and self-healing cells were developed that can be handled as conventional logic within the design flow. The feasibility of the approach is verified by a first prototype implementation of a fault tolerant adder circuit.","PeriodicalId":297689,"journal":{"name":"2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124804655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

The HDL and FE Thermal Modeling of Heterogeneous Systems 非均质系统的HDL和FE热模拟

2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2008-04-16 DOI: 10.1109/DDECS.2008.4538769

G. Janczyk, T. Bieniek

引用次数: 0

A System-On-Chip for Wireless Body Area Sensor Network Node 一种用于无线身体区域传感器网络节点的片上系统

2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2008-04-16 DOI: 10.1109/DDECS.2008.4538770

Z. Stamenkovic, G. Panic, G. Schoof

引用次数: 6

Code Coverage Analysis using High-Level Decision Diagrams 使用高级决策图的代码覆盖率分析

2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2008-04-16 DOI: 10.1109/DDECS.2008.4538786

J. Raik, U. Reinsalu, R. Ubar, M. Jenihhin, P. Ellervee

引用次数: 14

Calculation of LFSR Seed and Polynomial Pair for BIST Applications BIST应用中LFSR种子和多项式对的计算

2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2008-04-16 DOI: 10.1109/DDECS.2008.4538801

A. Jutman, A. Tsertov, R. Ubar

{"title":"Calculation of LFSR Seed and Polynomial Pair for BIST Applications","authors":"A. Jutman, A. Tsertov, R. Ubar","doi":"10.1109/DDECS.2008.4538801","DOIUrl":"https://doi.org/10.1109/DDECS.2008.4538801","url":null,"abstract":"Polynomial selection for LFSR-based BIST schemes has been typically left out of the scope of active research in the recent works due to lack of analytical methods that address this issue. Usage of primitive polynomial with a small number of feedbacks is considered a classical rule of thumb that is usually implemented. Although being beneficial for very long test sequences, primitive polynomial cannot guarantee fast fault coverage growth, which is a critical issue in pseudo-random-pattern-generator-based embedded test approaches. Hence, selecting a good initial state would be the main instrument for getting the fast coverage gain. In this work, we propose a formal analytical method to calculate a customized polynomial and seed pair for each separate design/test case. This novel technique allows shortening BIST runtimes and increasing fault coverage by embedding given efficient test patterns into the LFSR sequence. Being used in mixed-mode BIST techniques, the method shows decreasing trend in test application time and/or necessary test pattern storage resources. Our comparison against primitive polynomial based sequences support these observations.","PeriodicalId":297689,"journal":{"name":"2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115835651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Novel Hardware Implementation of Adaptive Median Filters 自适应中值滤波器的新型硬件实现

2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2008-04-16 DOI: 10.1109/DDECS.2008.4538766

Z. Vašíček, L. Sekanina

引用次数: 78

Portable Measurement Equipment for Continuous Biomedical Monitoring using Microelectrodes 用于微电极连续生物医学监测的便携式测量设备

2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2008-04-16 DOI: 10.1109/DDECS.2008.4538750

L. Majer, V. Stopjaková

引用次数: 4

A Trapezoidal Approach to Corner Stitching Data Structures for Arbitrary Routing Angles 任意路径角角拼接数据结构的梯形方法

2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2008-04-16 DOI: 10.1109/DDECS.2008.4538756

T. Jambor, D. Zaum, M. Olbrich, E. Barke

引用次数: 1

Cryptographic System on a Chip based on Actel ARM7 Soft-Core with Embedded True Random Number Generator 基于Actel ARM7软核的嵌入式真随机数生成器芯片密码系统

2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2008-04-16 DOI: 10.1109/DDECS.2008.4538778

M. Drutarovský, M. Varchola

引用次数: 13