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2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems最新文献

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Low-Voltage Low-Power Highly Linear Down-Sampling Mixer in 65nm Digital CMOS Technology 基于65nm数字CMOS技术的低压低功耗高线性下采样混频器
2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2008-04-16 DOI: 10.1109/DDECS.2008.4538780
K. Schweiger, H. Zimmermann
{"title":"Low-Voltage Low-Power Highly Linear Down-Sampling Mixer in 65nm Digital CMOS Technology","authors":"K. Schweiger, H. Zimmermann","doi":"10.1109/DDECS.2008.4538780","DOIUrl":"https://doi.org/10.1109/DDECS.2008.4538780","url":null,"abstract":"A highly linear down-conversion mixer in a 65 nm digital CMOS technology is presented. The mixer was fabricated in a tripple-well process which allows to use the bulk of NMOS transistors as inputs. In contrary to other works not the gate but the bulk connector is used for the input signal. A high IIP3 of +18 dBm was achieved with a power consumption of only 0.67 mW from a 1.2 V supply voltage. The mixer has a measured ldB compression point of +7 dBm. The input signal bandwidth lies beyond 2 GHz.","PeriodicalId":297689,"journal":{"name":"2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128861941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Software-Based Self-Test Strategy for Data Cache Memories Embedded in SoCs 基于软件的soc数据缓存存储器自检策略
2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2008-04-16 DOI: 10.1109/DDECS.2008.4538813
H. WilsonJ.Pérez, J. Velasco-Medina, D. Ravotto, E. Sánchez, M. Reorda
{"title":"Software-Based Self-Test Strategy for Data Cache Memories Embedded in SoCs","authors":"H. WilsonJ.Pérez, J. Velasco-Medina, D. Ravotto, E. Sánchez, M. Reorda","doi":"10.1109/DDECS.2008.4538813","DOIUrl":"https://doi.org/10.1109/DDECS.2008.4538813","url":null,"abstract":"Testing SoC is a challenging task, especially when addressing complex and high- frequency devices. Among the different techniques that can be exploited, software-based selft-test (SBST) emerged as an effective solution, due some advantages it provides (no HW changes, at- speed testing, re-usability); however, the method requires effective techniques for generating suitable test programs. In this paper we face the issue of generating programs to test data caches (in particular their control part): a method is proposed, and some experimental results are provided to assess its effectiveness.","PeriodicalId":297689,"journal":{"name":"2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121524174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Ad-Hoc Translations to Close Verilog Semantics Gap Ad-Hoc翻译关闭Verilog语义差距
2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2008-04-16 DOI: 10.1109/DDECS.2008.4538785
Christian Haufe, Frank Rogin
{"title":"Ad-Hoc Translations to Close Verilog Semantics Gap","authors":"Christian Haufe, Frank Rogin","doi":"10.1109/DDECS.2008.4538785","DOIUrl":"https://doi.org/10.1109/DDECS.2008.4538785","url":null,"abstract":"This paper describes rules to transform Verilog HDL source code in order to propagate X-values on RTL models in a more realistic way, and to check for potential differences of RTL simulation results against expected silicon implementation behavior. By running X-propagation simulations in parallel to usual RTL simulation and debugging, RTL design bugs previously detected in gate-level simulations can be detected earlier now. A prototypical tool automatically implements the proposed transformation rules. Experimental results on two industrial hardware designs validate the usefulness of our approach and justify its application in everyday use.","PeriodicalId":297689,"journal":{"name":"2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122881627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Temperature-Aware Task Mapping for Energy Optimization with Dynamic Voltage Scaling 基于温度感知的动态电压标度能量优化任务映射
2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2008-04-16 DOI: 10.1109/DDECS.2008.4538754
Min Bao, A. Andrei, P. Eles, Zebo Peng
{"title":"Temperature-Aware Task Mapping for Energy Optimization with Dynamic Voltage Scaling","authors":"Min Bao, A. Andrei, P. Eles, Zebo Peng","doi":"10.1109/DDECS.2008.4538754","DOIUrl":"https://doi.org/10.1109/DDECS.2008.4538754","url":null,"abstract":"Temperature has become an important issue in nowadays MPSoCs design due to the ever increasing power densities and huge energy consumption. This paper proposes a temperature-aware task mapping technique for energy optimization in systems with dynamic voltage selection capability. It evaluates the efficiency of this technique, based on the analysis of the factors that can influence the potential gains that can be expected from such a technique, compared to a task mapping approach that ignores temperature.","PeriodicalId":297689,"journal":{"name":"2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115521346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Calculating the fault coverage for dual neighboring faults using single stuck-at fault patterns 利用单卡滞故障模式计算双相邻故障的故障覆盖率
2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2008-04-16 DOI: 10.1109/DDECS.2008.4538792
J. Schat
{"title":"Calculating the fault coverage for dual neighboring faults using single stuck-at fault patterns","authors":"J. Schat","doi":"10.1109/DDECS.2008.4538792","DOIUrl":"https://doi.org/10.1109/DDECS.2008.4538792","url":null,"abstract":"Chip structures shrink rapidly, but the particles causing the defects do not shrink in the same degree, thus multiple faults are more and more frequent in today's deep sub-micron chips. Scan test patterns are usually calculated to detect single stuck-at faults, and they detect also 'nearly all' multiple faults if at least one of the faults is detectable as a single fault. 'Nearly all' implies that there are exceptions, and indeed sometimes two single-stuck-at faults can only be detected when occurring alone, but not if they occur together. This phenomenon is called fault masking and has been extensively discussed in the literature, but only in considering each pair of possible faults having the same likelihood to occur. In reality, however, pairs of neighboring faults have a much higher likelihood than pairs of distant faults. Using layout and pattern data of a commercial circuit, the extent of fault masking is calculated both for neighboring faults, and for distant faults.","PeriodicalId":297689,"journal":{"name":"2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems","volume":"183 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123335639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Efficient Allocation of Verification Resources using Revision History Information 利用修订历史信息有效分配验证资源
2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2008-04-16 DOI: 10.1109/DDECS.2008.4538784
J. Nacif, Thiago S. F. Silva, Andréa Iabrudi Tavares, A. O. Fernandes, C. Coelho
{"title":"Efficient Allocation of Verification Resources using Revision History Information","authors":"J. Nacif, Thiago S. F. Silva, Andréa Iabrudi Tavares, A. O. Fernandes, C. Coelho","doi":"10.1109/DDECS.2008.4538784","DOIUrl":"https://doi.org/10.1109/DDECS.2008.4538784","url":null,"abstract":"Verifying large industrial designs is getting harder each day. The current verification methodologies are not able to guarantee bug free designs. Some recurrent questions during a design verification are: Which modules are most likely to contain undetected bugs? In which modules the verification team should concentrate their effort? This information is very useful, because it is better to start verifying the most bug-prone modules. In this work we present a novel approach to answer these questions. In order to identify these bug-prone modules, the revision history of the design is used. Using information of an academic experiment, we demonstrate that there is a close relationship between bugs/changes history and future bugs. Our results show that allocating modules for verification based on bugs/changes leaded to the coverage of 91.67% of future bugs, while random based strategy covered only 37.5% of the future bugs.","PeriodicalId":297689,"journal":{"name":"2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125396435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Gain reduction by gate-leakage currents in regulated cascodes 通过调节级联码中的栅漏电流降低增益
2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2008-04-16 DOI: 10.1109/DDECS.2008.4538755
Franz Schlögl, K. Schneider-Hornstein, H. Zimmermann
{"title":"Gain reduction by gate-leakage currents in regulated cascodes","authors":"Franz Schlögl, K. Schneider-Hornstein, H. Zimmermann","doi":"10.1109/DDECS.2008.4538755","DOIUrl":"https://doi.org/10.1109/DDECS.2008.4538755","url":null,"abstract":"The gain reduction of nanometer-size MOS transistors due to the high output conductance of the devices is already discussed in the literature. This paper discusses an additional issue which leads to further gain reduction - the gate-leakage current. On the basis of the example of a regulated cascode in 130 nm CMOS and in 65 nm CMOS it is estimated that this shrinking step decreases the gain due to gate-leakage current by about 30 to 40 dB.","PeriodicalId":297689,"journal":{"name":"2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128070721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Deep-Submicron MOS Transistor Matching: A Case Study 深亚微米MOS晶体管匹配:一个案例研究
2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2008-04-16 DOI: 10.1109/DDECS.2008.4538744
D. Dimitrov
{"title":"Deep-Submicron MOS Transistor Matching: A Case Study","authors":"D. Dimitrov","doi":"10.1109/DDECS.2008.4538744","DOIUrl":"https://doi.org/10.1109/DDECS.2008.4538744","url":null,"abstract":"This article sets out to evaluate the MOS transistor mismatch in a standard 0.18 mum CMOS technology. It compares different methods for extracting MOS transistor matching parameters, and analyzes the drain current matching in detail. Test results are presented and analyzed.","PeriodicalId":297689,"journal":{"name":"2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems","volume":"171 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121278946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Web-Based Framework for Parallel Distributed Test 基于web的并行分布式测试框架
2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2008-04-16 DOI: 10.1109/DDECS.2008.4538800
E. Ivask, J. Raik, R. Ubar
{"title":"Web-Based Framework for Parallel Distributed Test","authors":"E. Ivask, J. Raik, R. Ubar","doi":"10.1109/DDECS.2008.4538800","DOIUrl":"https://doi.org/10.1109/DDECS.2008.4538800","url":null,"abstract":"In this paper we describe Web-based distributed system suitable for acceleration of fault simulation in digital circuits. Framework has three-tier client server concept. Java applets are used for user interfaces. Java servlet on master server supports communication, task partitioning, user tracking, data management, etc. HTTP protocol based solution is used, since it is well established and flexible in firewall- protected environments. Reuse of existing test tools by encapsulation into Java agents extends the lifecycle and value of these tools. Considerable fault simulation speedup was gained in experiments. Two types of fault set partitioning were tried: adjacent fault selection and random fault selection. The latter is able to ensure more equal execution times for subtasks and therefore contributes to overall shorter parallel simulation time.","PeriodicalId":297689,"journal":{"name":"2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127977007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
MPEG-based Performance Comparison between Network-on-Chip and AMBA MPSoC 基于mpeg的片上网络与AMBA的MPSoC性能比较
2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2008-04-16 DOI: 10.1109/DDECS.2008.4538764
R. Shafik, P. Rosinger, B. Al-Hashimi
{"title":"MPEG-based Performance Comparison between Network-on-Chip and AMBA MPSoC","authors":"R. Shafik, P. Rosinger, B. Al-Hashimi","doi":"10.1109/DDECS.2008.4538764","DOIUrl":"https://doi.org/10.1109/DDECS.2008.4538764","url":null,"abstract":"Using analytical and simulation results, this paper presents comparative analyses between network on chip and shared-bus AMBA using real application traffic with MPEG-2 video decoder in cycle-accurate realistic simulation environment. We show that despite higher channel latency, NoC has higher bandwidth advantage and outperforms shared-bus AMBA, requiring lower frequency in order to decode the video bitstream at given frame rate.","PeriodicalId":297689,"journal":{"name":"2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114926792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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