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Analysis of the influence of intermittent faults in a microcontroller 单片机间歇故障的影响分析
2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2008-04-16 DOI: 10.1109/DDECS.2008.4538761
J. Gracia, L. J. Saiz, J. Baraza, D. Gil, P. Gil
{"title":"Analysis of the influence of intermittent faults in a microcontroller","authors":"J. Gracia, L. J. Saiz, J. Baraza, D. Gil, P. Gil","doi":"10.1109/DDECS.2008.4538761","DOIUrl":"https://doi.org/10.1109/DDECS.2008.4538761","url":null,"abstract":"Nowadays, new submicron technologies have allowed increasing processors performance while decreasing their size. However, as a side effect, their reliability has been negatively affected. Although mainly permanent and transient faults have been studied, intermittent faults are expected to be a big challenge in modern VLSI circuits. Usually, intermittent faults have been assumed to be the prelude of permanent faults. Currently, intermittent faults due to process variations and residues have grown, being necessary to study their effects. The objective of this work has been to analyse the impact of intermittent faults, taking advantage of the power of the simulation-based fault injection methodology. Using as background faults observed in real computer systems, we have injected intermittent faults in the VHDL model of a microcontroller. The controllability and flexibility of VHDL- based fault injection technique has allowed us to do a detailed analysis of the influence of some parameters of intermittent faults. We have also compared the results obtained with the impact of transient and permanent faults.","PeriodicalId":297689,"journal":{"name":"2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124005218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 38
SoCECT: System on Chip Embedded Core Test SoCECT:片上系统嵌入式核心测试
2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2008-04-16 DOI: 10.1109/DDECS.2008.4538811
Michael Higgins, Ciaran MacNamee, Brendan Mullane
{"title":"SoCECT: System on Chip Embedded Core Test","authors":"Michael Higgins, Ciaran MacNamee, Brendan Mullane","doi":"10.1109/DDECS.2008.4538811","DOIUrl":"https://doi.org/10.1109/DDECS.2008.4538811","url":null,"abstract":"This paper presents SoCECT (system on chip embedded core test), a novel test controller architecture that allows multiple IEEE 1500 wrapped cores within a SoC to be tested concurrently. SoCECT makes use of the IEEE 1149.1 JTAG state machine to operate the test controller and also to allow for future integration with an IEEE P1687 interface. SoCECT also includes a test access mechanism (TAM) methodology(distributed architecture) that reuses the physical connections of the SoC system bus to provide an efficient transport medium for structural and functional test vectors between the embedded test controller and IEEE 1500 wrapped cores.","PeriodicalId":297689,"journal":{"name":"2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems","volume":"07 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127197621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Built-In Current Monitor for IDDQ Testing in CMOS 90 nm Technology 内置电流监视器在CMOS 90纳米技术IDDQ测试
2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2008-04-16 DOI: 10.1109/DDECS.2008.4538797
Marcin J. Beresinski, T. Borejko, W. Pleskacz, V. Stopjaková
{"title":"Built-In Current Monitor for IDDQ Testing in CMOS 90 nm Technology","authors":"Marcin J. Beresinski, T. Borejko, W. Pleskacz, V. Stopjaková","doi":"10.1109/DDECS.2008.4538797","DOIUrl":"https://doi.org/10.1109/DDECS.2008.4538797","url":null,"abstract":"In this paper, a built-in current (BIC) monitor for testing low-voltage digital CMOS circuits is presented. The monitor is designated for typical IDDQ testing as well as for characterization of supply current values for different test vectors. Voltage drop across the monitor during measurement and the switching phase are minimized. A wide range of currents is supported. Abilities and limitations of the BIC monitor were verified through simulations. Results of post layout simulations are presented as well. The design was implemented in UMC CMOS 90 nm technology.","PeriodicalId":297689,"journal":{"name":"2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130892649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Efficient Estimation of Die-Level Process Parameter Variations via the EM-Algorithm 基于em算法的模具级工艺参数变化的有效估计
2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2008-04-16 DOI: 10.1109/DDECS.2008.4538804
A. Zjajo, Shaji Krishnan, J. P. D. Gyvez
{"title":"Efficient Estimation of Die-Level Process Parameter Variations via the EM-Algorithm","authors":"A. Zjajo, Shaji Krishnan, J. P. D. Gyvez","doi":"10.1109/DDECS.2008.4538804","DOIUrl":"https://doi.org/10.1109/DDECS.2008.4538804","url":null,"abstract":"A new approach for efficient estimation of die-level process parameter variations based on the expectation- maximization algorithm is proposed. To estimate the parameters and enhance diagnostic analysis, dedicated embedded sensors have been designed. Additionally, to guide the test with the information obtained through monitoring process variations, maximum-likelihood method and adjusted support vector machine classifier is employed. The information acquired is re-used and supplement the circuit calibration. The proposed estimation method is evaluated on a prototype ADC converter with dedicated sensors fabricated in standard single poly, five metal 0.09-mum CMOS.","PeriodicalId":297689,"journal":{"name":"2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134443160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
SoC Symbolic Simulation: a case study on delay fault testing SoC符号仿真:延迟故障测试案例研究
2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2008-04-16 DOI: 10.1109/DDECS.2008.4538810
A. Bosio, P. Girard, S. Pravossoudovitch, P. Bernardi
{"title":"SoC Symbolic Simulation: a case study on delay fault testing","authors":"A. Bosio, P. Girard, S. Pravossoudovitch, P. Bernardi","doi":"10.1109/DDECS.2008.4538810","DOIUrl":"https://doi.org/10.1109/DDECS.2008.4538810","url":null,"abstract":"Functional test methodologies such as software-based self-test appear to suit well SoC delay fault testing. State-of-the-art solutions in this topic are quite far from maturity and few works consider software-based diagnosis for delay faults. In this paper we evaluate benefits and costs in using symbolic simulation for SoCs, in particular focusing on embedded processor core testing. Symbolic simulation principles are key to enable fast analysis and speed up delay fault diagnosis; to cope with SoC behavior, the traditional 6-valued symbolic algebra was expanded in order to tackle X and Z logic states. As a case study we consider a large design including many core types and suitable DFT for performing high quality test without scan chains.","PeriodicalId":297689,"journal":{"name":"2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132772761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Experimental Analog Circuit for Parametric Test Methods Efficiency Evaluation 实验模拟电路参数化测试方法效率评价
2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2008-04-16 DOI: 10.1109/DDECS.2008.4538805
J. Brenkus, V. Stopjaková, J. Mihálov
{"title":"Experimental Analog Circuit for Parametric Test Methods Efficiency Evaluation","authors":"J. Brenkus, V. Stopjaková, J. Mihálov","doi":"10.1109/DDECS.2008.4538805","DOIUrl":"https://doi.org/10.1109/DDECS.2008.4538805","url":null,"abstract":"An experimental analog design for parametric test methods efficiency evaluation is presented. The circuit is implemented in a standard 0.35 mum CMOS process by AMS. The circuit under test (CUT) is a two-stage operational amplifier with implemented addressable faults. The control of the overall circuit is ensured by a 7-bit shift register. For higher loading capability a buffer is connected to the output. To preserve the possibility of voltage ramping, the CUT has a separated supply rail. The CUT can be also connected to a feedback network integrated on the chip, and thus, turned into an oscillator.","PeriodicalId":297689,"journal":{"name":"2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117081357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Partial Scan Based Test Generation for Asynchronous Circuits 基于部分扫描的异步电路测试生成
2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2008-04-16 DOI: 10.1109/DDECS.2008.4538783
D. Vasudevan, A. Efthymiou
{"title":"A Partial Scan Based Test Generation for Asynchronous Circuits","authors":"D. Vasudevan, A. Efthymiou","doi":"10.1109/DDECS.2008.4538783","DOIUrl":"https://doi.org/10.1109/DDECS.2008.4538783","url":null,"abstract":"Test Generation for asynchronous circuit is a hard problem mainly due to the absence of a global clock. Full scan design based test generation of asynchronous circuits seems to be feasible but at an expense of large area overhead. Partial scan should be a better option with lower area overhead but there is no known systematic way of selecting which asynchronous state-holding elements to scan. This paper presents a partial scan and automatic test generation methodology based on a novel adaptation of BALLAST for asynchronous circuits and time frame unrolling. Balanced structures are used to guide the selection of the state-holding elements that will be scanned. A cyclic to acyclic conversion of the input circuit is used to create a combinational circuit for which test patterns are easily generated using well known methods. These test patterns are then used to test the original circuit. Fault coverage and area overhead results of this method are obtained and analyzed with full scan and other methods.","PeriodicalId":297689,"journal":{"name":"2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132310166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Rapid Prototyping of NoC Architectures from a SystemC Specification 基于系统规范的NoC架构快速原型设计
2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2008-04-16 DOI: 10.1109/DDECS.2008.4538765
S. Deniziak, R. Tomaszewski
{"title":"Rapid Prototyping of NoC Architectures from a SystemC Specification","authors":"S. Deniziak, R. Tomaszewski","doi":"10.1109/DDECS.2008.4538765","DOIUrl":"https://doi.org/10.1109/DDECS.2008.4538765","url":null,"abstract":"This work presents a methodology for mapping of a SystemC specification onto a given Network-on-Chip (NoC) architecture, for the purpose of FPGA prototyping. A communication protocol and routing tables are generated automatically by using inter-module communication analysis. For each processor in the target architecture, assigned SystemC processes are converted into C++ programs, where all communication method calls are replaced with sending/receiving messages to/from the network interface (NI) process. For each module implemented in hardware a VHDL code of the NI is generated. NIs convert transmitted data into/from network packets according to the communication protocol. Presented embedded HTTP server example substantiates the benefits of the methodology.","PeriodicalId":297689,"journal":{"name":"2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127283446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Incremental SAT Instance Generation for SAT-based ATPG 基于SAT的ATPG增量SAT实例生成
2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2008-04-16 DOI: 10.1109/DDECS.2008.4538759
Daniel Tille, R. Drechsler
{"title":"Incremental SAT Instance Generation for SAT-based ATPG","authors":"Daniel Tille, R. Drechsler","doi":"10.1109/DDECS.2008.4538759","DOIUrl":"https://doi.org/10.1109/DDECS.2008.4538759","url":null,"abstract":"Due to ever increasing design sizes more efficient tools for automatic test pattern generation (ATPG) are needed. Recently ATPG based on Boolean satisfiability (SAT) has been shown to be a beneficial complement to traditional ATPG techniques. This paper makes two contributions. Firstly, we analyze the two steps SAT-based ATPG consists of with respect to their run time on industrial benchmarks. Secondly, exploiting these analysis results, we propose an incremental solving technique with the objective to speed up the entire classification process. An experimental evaluation of the proposed method shows a significant reduction of the overall run time of the SAT- based ATPG process.","PeriodicalId":297689,"journal":{"name":"2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128796867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
An Integrated Input Encoding and Symbolic Functional Decomposition for LUT-Based FPGAs 基于lut的fpga集成输入编码与符号功能分解
2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2008-04-16 DOI: 10.1109/DDECS.2008.4538749
S. Deniziak, M. Wisniewski
{"title":"An Integrated Input Encoding and Symbolic Functional Decomposition for LUT-Based FPGAs","authors":"S. Deniziak, M. Wisniewski","doi":"10.1109/DDECS.2008.4538749","DOIUrl":"https://doi.org/10.1109/DDECS.2008.4538749","url":null,"abstract":"In this paper a method for decomposition of functions with multi-valued inputs is presented. Decomposition is performed simultaneously with encoding of symbolic values. In this way an impact of input encoding on decomposition efficiency is taken into consideration during optimization. The goal of our method is to find encoding that maximally simplifies functional decomposition. Experimental results showed that the presented method significantly reduces the cost of FPGA implementations for most evaluated benchmarks.","PeriodicalId":297689,"journal":{"name":"2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121807530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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