Novel Hardware Implementation of Adaptive Median Filters

Abstract

A new FPGA implementation for adaptive median filters is proposed. Adaptive median filters exhibit better filtering properties than standard median filters; however, their implementation cost is higher. Proposed architecture was optimized for throughput allowing 300 M pixels to be filtered per second. The best performance/cost ratio exhibits the adaptive median filter which utilizes filtering window 7x7 pixels and can suppress shot noise with intensity up to 60%. In addition to filtering, adaptive median filters can be also used as detectors of corrupted pixels (detection statistics).