2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)最新文献_第8页

A low voltage buck DC-DC converter using on-chip gate boost technique in 40nm CMOS 采用片上栅极升压技术的40nm CMOS低压降压DC-DC变换器

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509580

Xin Zhang, Po-Hung Chen, Y. Ryu, K. Ishida, Yasuyuki Okuma, Kazunori Watanabe, T. Sakurai, M. Takamiya

引用次数: 1

SMYLE OpenCL: A programming framework for embedded many-core SoCs SMYLE OpenCL:用于嵌入式多核soc的编程框架

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509657

H. Tomiyama, Takuji Hieda, N. Nishiyama, Noriko Etani, Ittetsu Taniguchi

引用次数: 8

Compact nonlinear thermal modeling of packaged integrated systems 封装集成系统的紧凑非线性热建模

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509589

Zao Liu, S. Tan, Hai Wang, S. Swarup, Ashish Gupta

{"title":"Compact nonlinear thermal modeling of packaged integrated systems","authors":"Zao Liu, S. Tan, Hai Wang, S. Swarup, Ashish Gupta","doi":"10.1109/ASPDAC.2013.6509589","DOIUrl":"https://doi.org/10.1109/ASPDAC.2013.6509589","url":null,"abstract":"This paper proposes a new thermal nonlinear modeling technique for packaged integrated systems. Thermal behavior of complicated systems like packaged electronic systems may exhibit nonlinear and temperature dependent properties. As a result, it is difficult to use a low order linear model to approximate the thermal behavior of the packaged integrated systems without accuracy loss. In this paper, we try to mitigate this problem by using piecewise linear (PWL) approach to characterizing the thermal behavior of those systems. The new method (called ThermSubPWL), which is the first proposed approach to nonlinear thermal modeling problem, identifies the linear local models for different temperature ranges using the subspace identification method. A linear transformation method is proposed to transform all the identified linear local models to the common state basis to build the continuous piecewise linear model. Experimental results validate the proposed method on a realistic packaged integrated system modeled via the multi-domain/physics commercial tool, COMSOL, under practical power signal inputs. The new piecewise models can lead to much smaller model order without accuracy loss, which translates to significant savings in both the simulation time and the time required to identify the reduced models compared to applying the high order models.","PeriodicalId":297528,"journal":{"name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122229989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

The Liquid Metal IP bridge

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509614

P. Cheng, Stephen J. Fink, R. Rabbah, Sunil Shukla

引用次数: 1

Block-level designs of die-to-wafer bonded 3D ICs and their design quality tradeoffs 芯片到晶圆键合3D集成电路的块级设计及其设计质量权衡

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509680

K. Athikulwongse, Daehyun Kim, Moongon Jung, S. Lim

引用次数: 7

Thermal-reliable 3D clock-tree synthesis considering nonlinear electrical-thermal-coupled TSV model 考虑非线性电-热耦合TSV模型的热可靠三维时钟树合成

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509681

Y. Shang, Chun Zhang, Hao Yu, Chuan-Seng Tan, Xin Zhao, S. Lim

引用次数: 23

Improving energy efficiency for energy harvesting embedded systems 提高能源收集嵌入式系统的能源效率

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509645

Yang Ge, Yukan Zhang, Qinru Qiu

引用次数: 7

Stable backward reachability correction for PLL verification with consideration of environmental noise induced jitter 考虑环境噪声诱发抖动的锁相环验证的稳定后向可达性校正

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509691

Yang Song, Haipeng Fu, Hao Yu, G. Shi

{"title":"Stable backward reachability correction for PLL verification with consideration of environmental noise induced jitter","authors":"Yang Song, Haipeng Fu, Hao Yu, G. Shi","doi":"10.1109/ASPDAC.2013.6509691","DOIUrl":"https://doi.org/10.1109/ASPDAC.2013.6509691","url":null,"abstract":"It is unknown to perform efficient PLL system-level verification with consideration of jitter induced by substrate or power-supply noise. With the consideration of nonlinear phase noise macromodel, this paper introduces a forward reachability analysis with stable backward correction for PLL system-level verification with jitter. By refining initial state of PLL through backward correction, one can perform an efficient PLL verification to automatically adjust the locking range with consideration of environmental noise induced jitter. Moreover, to overcome the unstable nature during backward correction, a stability calibration is introduced in this paper to limit error. To validate our method, the proposed approach is applied to verify a number of PLL designs including single-LC or coupled-LC oscillators described by system-level behavioral model with jitter. Experimental results show that our forward reachability analysis with backward correction can succeed in reaching the adjusted locking range by correcting initial states in presence of environmental noise induced jitter.","PeriodicalId":297528,"journal":{"name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126276850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Variability-aware memory management for nanoscale computing 纳米级计算的可变性感知内存管理

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509584

N. Dutt, Puneet Gupta, A. Nicolau, L. A. Bathen, Mark Gottscho

引用次数: 11

315MHz OOK transceiver with 38-µW receiver and 36-µW transmitter in 40-nm CMOS 315MHz OOK收发器，38µW接收器和36µW发射器，40nm CMOS

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509572

S. Iguchi, Akira Saito, Kentaro Honda, Y. Zheng, Kazunori Watanabe, T. Sakurai, M. Takamiya

引用次数: 0