2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)最新文献_第7页

A full 4-channel 60 GHz direct-conversion transceiver 一个完整的4通道60 GHz直接转换收发器

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509573

Seitaro Kawai, R. Minami, Ahmed Musa, Takahiro Sato, Ning Li, Tatsuya Yamaguchi, Y. Takeuchi, Yuki Tsukui, K. Okada, A. Matsuzawa

引用次数: 14

BAMSE: A balanced mapping space exploration algorithm for GALS-based manycore platforms BAMSE:一种基于gis的多核平台平衡映射空间探索算法

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509642

Mohammad H. Foroozannejad, Brent Bohnenstiehl, S. Ghiasi

引用次数: 1

A physical unclonable function chip exploiting load transistors' variation in SRAM bitcells 一种利用SRAM位元中负载晶体管变化的物理不可克隆功能芯片

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509565

S. Okumura, S. Yoshimoto, H. Kawaguchi, M. Yoshimoto

引用次数: 3

Symmetrical buffered clock-tree synthesis with supply-voltage alignment 具有电源电压对准的对称缓冲时钟树合成

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509637

Xin-Wei Shih, Tzu-Hsuan Hsu, Hsu-Chieh Lee, Yao-Wen Chang, Kai-Yuan Chao

{"title":"Symmetrical buffered clock-tree synthesis with supply-voltage alignment","authors":"Xin-Wei Shih, Tzu-Hsuan Hsu, Hsu-Chieh Lee, Yao-Wen Chang, Kai-Yuan Chao","doi":"10.1109/ASPDAC.2013.6509637","DOIUrl":"https://doi.org/10.1109/ASPDAC.2013.6509637","url":null,"abstract":"For high-performance synchronous systems, non-uniform/non-ideal supply voltages of buffers (e.g., due to IRdrop) may incur a large clock skew and thus serious performance degradation. This paper addresses this problem and presents the first symmetrical buffered clock-tree synthesis flow that considers supply voltage differences of buffers. We employ a two-phase technique of bottom-up clock sink clustering to determine the tree topology, followed by top-down buffer placement and wire routing to complete the clock tree. At each level of processing, clock skew and wirelength are minimized by the determination of buffer embedding regions and the alignment of buffer supply voltages. Experimental results show that our method can reach, on average, respective 76% and 40% clock skew reduction compared to the state-of-the-art work (1) without supply voltage consideration and (2) with an extension for supply voltages based on our top-down flow. The reduction is achieved by marginal resource and runtime overheads. Note that our method can meet the stringent skew constraint set by the 2010 ISPD contest for all cases, while other counterparts cannot. In particular, our work provides a key insight into the importance of handling practical design issues (such as IR-drop) for real-world clock-tree synthesis.","PeriodicalId":297528,"journal":{"name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129456706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Dependable VLSI Platform using Robust Fabrics 采用稳健结构的可靠VLSI平台

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509583

H. Onodera

引用次数: 0

Pulsed-latch ASIC synthesis in industrial design flow 工业设计流程中的脉冲锁存器ASIC合成

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509621

Sangmin Kim, Duckhwan Kim, Youngsoo Shin

引用次数: 0

Optimizing routability in large-scale mixed-size placement 大规模混合尺寸布局的可达性优化

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509636

J. Cong, Guojie Luo, Kalliopi Tsota, Bingjun Xiao

{"title":"Optimizing routability in large-scale mixed-size placement","authors":"J. Cong, Guojie Luo, Kalliopi Tsota, Bingjun Xiao","doi":"10.1109/ASPDAC.2013.6509636","DOIUrl":"https://doi.org/10.1109/ASPDAC.2013.6509636","url":null,"abstract":"One of the necessary requirements for the placement process is that it should be capable of generating routable solutions. This paper describes a simple but effective method leading to the reduction of the routing congestion and the final routed wirelength for large-scale mixed-size designs. In order to reduce routing congestion and improve routability, we propose blocking narrow regions on the chip. We also propose dummy-cell insertion inside regions characterized by reduced fixed-macro density. Our placer consists of three major components: (i) narrow channel reduction by performing neighbor-based fixed-macro inflation; (ii) dummy-cell insertion inside large regions with reduced fixed-macro density; and (iii) pre-placement inflation by detecting tangled logic structures in the netlist and minimizing the maximum pin density. We evaluated the quality of our placer using the newly released DAC 2012 routability-driven placement contest designs and we compared our results to the top four teams that participated in the placement contest. The experimental results reveal that our placer improves the routability of the DAC 2012 placement contest designs and effectively reduces the routing congestion.","PeriodicalId":297528,"journal":{"name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"130 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116578379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 23

On real-time STM concurrency control for embedded software with improved schedulability 改进可调度性的嵌入式软件实时STM并发控制研究

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509557

Mohammed El-Shambakey, B. Ravindran

引用次数: 8

Network flow modeling for escape routing on staggered pin arrays 交错引脚阵列上逃逸路由的网络流建模

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509595

Pei-Ci Wu, Martin D. F. Wong

引用次数: 5

Shared cache aware task mapping for WCRT minimization 共享缓存感知任务映射，实现 WCRT 最小化

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509688

Huping Ding, Yun Liang, T. Mitra

引用次数: 20