2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)最新文献

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Maximizing return on investment of a grid-connected hybrid electrical energy storage system 并网混合电力储能系统的投资回报最大化
2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509670
Di Zhu, Yanzhi Wang, Siyu Yue, Q. Xie, Massoud Pedram, N. Chang
{"title":"Maximizing return on investment of a grid-connected hybrid electrical energy storage system","authors":"Di Zhu, Yanzhi Wang, Siyu Yue, Q. Xie, Massoud Pedram, N. Chang","doi":"10.1109/ASPDAC.2013.6509670","DOIUrl":"https://doi.org/10.1109/ASPDAC.2013.6509670","url":null,"abstract":"This paper is the first to present a comprehensive analysis of the profitability of the hybrid electrical energy storage (HEES) systems while further providing a HEES design and control optimization framework to maximize the total return on investment (ROI). The solution consists of two steps: (i) Derivation of an optimal HEES management policy to maximize the daily energy cost saving and (ii) Optimal design of the HEES system to maximize the amortized annual profit under budget and system volume constraints. We consider a HEES system comprised of lead-acid and Li-ion batteries for a case study. The optimal HEES system achieves an annual ROI of up to 60% higher than a lead-acid battery-only system (Li-ion battery-only) system.","PeriodicalId":297528,"journal":{"name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"497 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123197543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
Schedule integration for time-triggered systems 时间触发系统的计划集成
2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509558
Florian Sagstetter, M. Lukasiewycz, S. Chakraborty
{"title":"Schedule integration for time-triggered systems","authors":"Florian Sagstetter, M. Lukasiewycz, S. Chakraborty","doi":"10.1109/ASPDAC.2013.6509558","DOIUrl":"https://doi.org/10.1109/ASPDAC.2013.6509558","url":null,"abstract":"This paper presents a framework for schedule integration of time-triggered systems tailored to the automotive domain. In-vehicle networks might be very large and complex and hence obtaining a schedule for a fully synchronous system becomes a challenging task since all bus and processor constraints as well as end-to-end-timing constraints have to be taken concurrently into account. Existing optimization approaches apply the schedule optimization to the entire network, limiting their application due to scalability issues. In contrast, the presented framework obtains the schedule for the entire network, using a two-step approach where for each cluster a local schedule is obtained first and the local schedules are then merged to the global schedule. This approach is also in accordance with the design process in the automotive industry where different subsystems are developed independently to reduce the design complexity and are finally combined in the integration stage. In this paper, a generic framework for schedule integration of time-triggered systems is presented. Further, we show how this framework is implemented for a FlexRay network using an Integer Linear Programming (ILP) approach which might also be easily adapted to other protocols. A realistic case study and a scalability analysis give evidence of the applicability and efficiency of our approach.","PeriodicalId":297528,"journal":{"name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"221 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123282410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A novel cell placement algorithm for flexible TFT circuit with mechanical strain and temperature consideration 一种考虑机械应变和温度的柔性TFT电路单元放置算法
2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509644
Jiun-Li Lin, Po-Hsun Wu, Tsung-Yi Ho
{"title":"A novel cell placement algorithm for flexible TFT circuit with mechanical strain and temperature consideration","authors":"Jiun-Li Lin, Po-Hsun Wu, Tsung-Yi Ho","doi":"10.1109/ASPDAC.2013.6509644","DOIUrl":"https://doi.org/10.1109/ASPDAC.2013.6509644","url":null,"abstract":"Mobility is the key device parameter to affect circuit performance in flexible thin-film transistor (TFT) technologies, and it is very sensitive to the change of mechanical strain and temperature. However, existing algorithms only consider the impact of mechanical strain in cell placement of flexible TFT circuit. Without taking temperature into consideration, mobility may be dramatically decreased which leads to circuit performance degradation. This paper presents the first work to reduce the mobility influence caused by the change of both mechanical strain and temperature. Experimental results show that the proposed algorithms can effectively reduce the chip temperature and the influence caused by mobility variation.","PeriodicalId":297528,"journal":{"name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125222228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Selectively protecting error-correcting code for area-efficient and reliable STT-RAM caches 选择性地保护纠错代码的区域效率和可靠的STT-RAM缓存
2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509610
Junwhan Ahn, S. Yoo, Kiyoung Choi
{"title":"Selectively protecting error-correcting code for area-efficient and reliable STT-RAM caches","authors":"Junwhan Ahn, S. Yoo, Kiyoung Choi","doi":"10.1109/ASPDAC.2013.6509610","DOIUrl":"https://doi.org/10.1109/ASPDAC.2013.6509610","url":null,"abstract":"Recent researches on STT-RAM revealed that device scaling makes its write operations unreliable. To mitigate the impact of this problem, this paper proposes a low-cost, ECC-based solution for STT-RAM caches. In particular, it proposes to share storage for ECC among different blocks within a set and to use them only for unsuccessful write operations. Experimental results show that our scheme reduces 74% to 98% of area overhead incurred by the conventional per-block ECC while maintaining system performance and reliability.","PeriodicalId":297528,"journal":{"name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127397715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Online estimation of the remaining energy capacity in mobile systems considering system-wide power consumption and battery characteristics 考虑全系统功耗和电池特性的移动系统剩余能量容量在线估计
2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509559
Donghwa Shin, Kitae Kim, N. Chang, Woojoo Lee, Yanzhi Wang, Q. Xie, Massoud Pedram
{"title":"Online estimation of the remaining energy capacity in mobile systems considering system-wide power consumption and battery characteristics","authors":"Donghwa Shin, Kitae Kim, N. Chang, Woojoo Lee, Yanzhi Wang, Q. Xie, Massoud Pedram","doi":"10.1109/ASPDAC.2013.6509559","DOIUrl":"https://doi.org/10.1109/ASPDAC.2013.6509559","url":null,"abstract":"Emerging mobile systems integrate a lot of functionality into a small form factor with a small energy source in the form of rechargeable battery. This situation necessitates accurate estimation of the remaining energy in the battery such that user applications can be judicious on how they consume this scarce and precious resource. This paper thus focuses on estimating the remaining battery energy in Android OS-based mobile systems. This paper proposes to instrument the Android kernel in order to collect and report accurate subsystem activity values based on real-time profiling of the running applications. The activity information along with offline-constructed, regression-based power macro models for major subsystems in the smartphone yield the power dissipation estimate for the whole system. Next, while accounting for the rate-capacity effect in batteries, the total power dissipation data is translated into the battery's energy depletion rate, and subsequently, used to compute the battery's remaining lifetime based on its current state of charge information. Finally, this paper describes a novel application design framework, which considers the batterys state-of-charge (SOC), batterys energy depletion rate, and service quality of the target application. The benefits of the design framework are illustrated by examining an archetypical case, involving the design space exploration and optimization of a GPS-based application in an Android OS.","PeriodicalId":297528,"journal":{"name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132262942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
High-throughput electron beam direct writing of VIA layers by character projection using character sets based on one-dimensional VIA arrays with area-efficient stencil design 基于一维VIA阵列的高通量电子束直接写入,采用面积高效的模板设计
2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509605
R. Ikeno, T. Maruyama, T. Iizuka, S. Komatsu, M. Ikeda, K. Asada
{"title":"High-throughput electron beam direct writing of VIA layers by character projection using character sets based on one-dimensional VIA arrays with area-efficient stencil design","authors":"R. Ikeno, T. Maruyama, T. Iizuka, S. Komatsu, M. Ikeda, K. Asada","doi":"10.1109/ASPDAC.2013.6509605","DOIUrl":"https://doi.org/10.1109/ASPDAC.2013.6509605","url":null,"abstract":"Character projection (CP) is a high-speed mask-less exposure technique for electron-beam direct writing (EBDW). In CP exposure of VIA layers, higher throughput is realized if more VIAs are exposed in each EB shot, but it will result in huge number of VIA characters required for arbitrary VIA placement. We adopt one-dimensional VIA array as the basic CP character architecture to increase VIA numbers in an EB shot while saving the stencil area by superposed character arrangement. CP throughput is further improved by layout constraints for VIA placement in detail routing phase. Our experimental results give estimated EB shot counts less than 174G shot/wafer in 14nm technologies.","PeriodicalId":297528,"journal":{"name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125590959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Native simulation of complex VLIW instruction sets using static binary translation and Hardware-Assisted Virtualization 使用静态二进制转换和硬件辅助虚拟化的复杂VLIW指令集的本地模拟
2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509660
M. M. Hamayun, F. Pétrot, Nicolas Fournel
{"title":"Native simulation of complex VLIW instruction sets using static binary translation and Hardware-Assisted Virtualization","authors":"M. M. Hamayun, F. Pétrot, Nicolas Fournel","doi":"10.1109/ASPDAC.2013.6509660","DOIUrl":"https://doi.org/10.1109/ASPDAC.2013.6509660","url":null,"abstract":"We introduce a static binary translation flow in native simulation context for cross-compiled VLIW executables. This approach is interesting in situations where either the source code is not available or the target platform is not supported by any retargetable compilation framework, which is usually the case for VLIW processors. The generated simulators execute on a Hardware-Assisted Virtualization (HAV) based native platform. We have implemented this approach for a TI C6x series processor and our simulation results show a speed-up of around two orders of magnitude compared to the cycle accurate simulators.","PeriodicalId":297528,"journal":{"name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127826914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Highly reliable solid-state drives (SSDs) with error-prediction LDPC (EP-LDPC) architecture and error-recovery scheme 具有错误预测LDPC (EP-LDPC)架构和错误恢复方案的高可靠性固态硬盘
2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509567
S. Tanakamaru, Y. Yanagihara, K. Takeuchi
{"title":"Highly reliable solid-state drives (SSDs) with error-prediction LDPC (EP-LDPC) architecture and error-recovery scheme","authors":"S. Tanakamaru, Y. Yanagihara, K. Takeuchi","doi":"10.1109/ASPDAC.2013.6509567","DOIUrl":"https://doi.org/10.1109/ASPDAC.2013.6509567","url":null,"abstract":"11-times extended lifetime, 76% reduced error SSD is proposed. The error-prediction LDPC realizes both 7-times faster read and high reliability. Errors are most efficiently corrected by calibrating memory data based on the VTH, inter-cell coupling, write/erase cycles and data-retention time. The error-recovery scheme with a program-disturb error-recovery pulse and a data-retention error-recovery pulse is also proposed to reduce the program-disturb error and the data-retention error by 76% and 56%, respectively.","PeriodicalId":297528,"journal":{"name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123192204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Design and verification tools for continuous fluid flow-based microfluidic devices 基于连续流体流动的微流体装置的设计和验证工具
2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509599
Jeffrey McDaniel, Auralila Baez, Brian Crites, Aditya Tammewar, P. Brisk
{"title":"Design and verification tools for continuous fluid flow-based microfluidic devices","authors":"Jeffrey McDaniel, Auralila Baez, Brian Crites, Aditya Tammewar, P. Brisk","doi":"10.1109/ASPDAC.2013.6509599","DOIUrl":"https://doi.org/10.1109/ASPDAC.2013.6509599","url":null,"abstract":"This paper describes an integrated design, verification, and simulation environment for programmable microfluidic devices called laboratories-on-chip (LoCs). Today's LoCs are architected and laid out by hand, which is time-consuming, tedious, and error-prone. To increase designer productivity, this paper introduces a Microfluidic Hardware Design Language (MHDL) for LoC specification, along with software tools to assist LoC designers verify the correctness of their specifications and estimate their performance.","PeriodicalId":297528,"journal":{"name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124509594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Sequential dependency and reliability analysis of embedded systems 嵌入式系统的顺序依赖与可靠性分析
2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509633
Hehua Zhang, Yu Jiang, Xiaoyu Song, W. Hung, M. Gu, Jiaguang Sun
{"title":"Sequential dependency and reliability analysis of embedded systems","authors":"Hehua Zhang, Yu Jiang, Xiaoyu Song, W. Hung, M. Gu, Jiaguang Sun","doi":"10.1109/ASPDAC.2013.6509633","DOIUrl":"https://doi.org/10.1109/ASPDAC.2013.6509633","url":null,"abstract":"Embedded systems are becoming increasingly popular due to their widespread applications and the reliability of them is a crucial issue. The complexity of the reliability analysis arises in handling the sequential feedback that make the system output depends not only on the present input but also the internal state. In this paper, we propose a novel probabilistic model, named sequential dependency model (SDM), for the reliability analysis of embedded systems with sequential feedback. It is constructed based on the structure of the system components and the signals among them. We prove that the SDM model is s Dynamic Bayesian Network (DBN) that captures: the spatial dependencies between system components in a single time slice, the temporal dependencies between system components of different time slices, and the temporal dependencies due to the sequential feedback. We initiate the conditional probability distribution (CPD) table of the SDM node with the failure probability of the corresponding system component. Then, the SDM model handles the spatial-temporal correlations at internal components as well as the higher order temporal correlations due to the sequential feedback with the computational mechanism of DBN, experiment results demonstrate the accuracy of our model.","PeriodicalId":297528,"journal":{"name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125372113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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