2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)最新文献_第10页

Reevaluating the latency claims of 3D stacked memories 重新评估3D堆叠存储器的延迟要求

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509675

D. W. Chang, Gyungsu Byun, Hoyoung Kim, Minwook Ahn, Soojung Ryu, N. Kim, M. Schulte

{"title":"Reevaluating the latency claims of 3D stacked memories","authors":"D. W. Chang, Gyungsu Byun, Hoyoung Kim, Minwook Ahn, Soojung Ryu, N. Kim, M. Schulte","doi":"10.1109/ASPDAC.2013.6509675","DOIUrl":"https://doi.org/10.1109/ASPDAC.2013.6509675","url":null,"abstract":"In recent years, 3D technology has been a popular area of study that has allowed researchers to explore a number of novel computer architectures. One of the more popular topics is that of integrating 3D main memory dies below the computing die and connecting them with through-silicon vias (TSVs). This is assumed to reduce off-chip main memory access latencies by roughly 45% to 60%. Our detailed circuit-level models, however, demonstrate that this latency reduction from the TSVs is significantly less. In this paper, we present these models, compare 2D and 3D main memory latencies, and show that the reduction in latency from using 3D main memory to be no more than 2.4 ns. We also show that although the wider I/O bus width enabled by using TSVs increases performance, it may do so with an increase in power consumption. Although TSVs consume less power per bit transfer than off-chip metal interconnects (11.2 times less power per bit transfer), TSVs typically use considerably more bits and may result in a net increase in power due to the large number of bits in the memory I/O bus. Our analysis shows that although a 3D memory hierarchy exploiting a wider memory bus can increase performance, this performance increase may not justify the net increase in power consumption.","PeriodicalId":297528,"journal":{"name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124904624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 25

A novel cell placement algorithm for flexible TFT circuit with mechanical strain and temperature consideration 一种考虑机械应变和温度的柔性TFT电路单元放置算法

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509644

Jiun-Li Lin, Po-Hsun Wu, Tsung-Yi Ho

引用次数: 4

Selectively protecting error-correcting code for area-efficient and reliable STT-RAM caches 选择性地保护纠错代码的区域效率和可靠的STT-RAM缓存

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509610

Junwhan Ahn, S. Yoo, Kiyoung Choi

引用次数: 15

Native simulation of complex VLIW instruction sets using static binary translation and Hardware-Assisted Virtualization 使用静态二进制转换和硬件辅助虚拟化的复杂VLIW指令集的本地模拟

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509660

M. M. Hamayun, F. Pétrot, Nicolas Fournel

引用次数: 7

High-throughput electron beam direct writing of VIA layers by character projection using character sets based on one-dimensional VIA arrays with area-efficient stencil design 基于一维VIA阵列的高通量电子束直接写入，采用面积高效的模板设计

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509605

R. Ikeno, T. Maruyama, T. Iizuka, S. Komatsu, M. Ikeda, K. Asada

引用次数: 7

Schedule integration for time-triggered systems 时间触发系统的计划集成

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509558

Florian Sagstetter, M. Lukasiewycz, S. Chakraborty

{"title":"Schedule integration for time-triggered systems","authors":"Florian Sagstetter, M. Lukasiewycz, S. Chakraborty","doi":"10.1109/ASPDAC.2013.6509558","DOIUrl":"https://doi.org/10.1109/ASPDAC.2013.6509558","url":null,"abstract":"This paper presents a framework for schedule integration of time-triggered systems tailored to the automotive domain. In-vehicle networks might be very large and complex and hence obtaining a schedule for a fully synchronous system becomes a challenging task since all bus and processor constraints as well as end-to-end-timing constraints have to be taken concurrently into account. Existing optimization approaches apply the schedule optimization to the entire network, limiting their application due to scalability issues. In contrast, the presented framework obtains the schedule for the entire network, using a two-step approach where for each cluster a local schedule is obtained first and the local schedules are then merged to the global schedule. This approach is also in accordance with the design process in the automotive industry where different subsystems are developed independently to reduce the design complexity and are finally combined in the integration stage. In this paper, a generic framework for schedule integration of time-triggered systems is presented. Further, we show how this framework is implemented for a FlexRay network using an Integer Linear Programming (ILP) approach which might also be easily adapted to other protocols. A realistic case study and a scalability analysis give evidence of the applicability and efficiency of our approach.","PeriodicalId":297528,"journal":{"name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"221 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123282410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Online estimation of the remaining energy capacity in mobile systems considering system-wide power consumption and battery characteristics 考虑全系统功耗和电池特性的移动系统剩余能量容量在线估计

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509559

Donghwa Shin, Kitae Kim, N. Chang, Woojoo Lee, Yanzhi Wang, Q. Xie, Massoud Pedram

{"title":"Online estimation of the remaining energy capacity in mobile systems considering system-wide power consumption and battery characteristics","authors":"Donghwa Shin, Kitae Kim, N. Chang, Woojoo Lee, Yanzhi Wang, Q. Xie, Massoud Pedram","doi":"10.1109/ASPDAC.2013.6509559","DOIUrl":"https://doi.org/10.1109/ASPDAC.2013.6509559","url":null,"abstract":"Emerging mobile systems integrate a lot of functionality into a small form factor with a small energy source in the form of rechargeable battery. This situation necessitates accurate estimation of the remaining energy in the battery such that user applications can be judicious on how they consume this scarce and precious resource. This paper thus focuses on estimating the remaining battery energy in Android OS-based mobile systems. This paper proposes to instrument the Android kernel in order to collect and report accurate subsystem activity values based on real-time profiling of the running applications. The activity information along with offline-constructed, regression-based power macro models for major subsystems in the smartphone yield the power dissipation estimate for the whole system. Next, while accounting for the rate-capacity effect in batteries, the total power dissipation data is translated into the battery's energy depletion rate, and subsequently, used to compute the battery's remaining lifetime based on its current state of charge information. Finally, this paper describes a novel application design framework, which considers the batterys state-of-charge (SOC), batterys energy depletion rate, and service quality of the target application. The benefits of the design framework are illustrated by examining an archetypical case, involving the design space exploration and optimization of a GPS-based application in an Android OS.","PeriodicalId":297528,"journal":{"name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132262942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 31

Design and verification tools for continuous fluid flow-based microfluidic devices 基于连续流体流动的微流体装置的设计和验证工具

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509599

Jeffrey McDaniel, Auralila Baez, Brian Crites, Aditya Tammewar, P. Brisk

引用次数: 21

An ILP-based automatic bus planner for dense PCBs 基于ilp的密集pcb自动总线规划器

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509593

Pei-Ci Wu, Q. Ma, Martin D. F. Wong

{"title":"An ILP-based automatic bus planner for dense PCBs","authors":"Pei-Ci Wu, Q. Ma, Martin D. F. Wong","doi":"10.1109/ASPDAC.2013.6509593","DOIUrl":"https://doi.org/10.1109/ASPDAC.2013.6509593","url":null,"abstract":"Modern PCBs have to be routed manually since no EDA tools can successfully route these complex boards. An auto-router for PCBs would improve design productivity tremendously since each board takes about 2 months to route manually. This paper focuses on a major step in PCB routing called bus planning. In the bus planning problem, we need to simultaneously solve the bus decomposition, escape routing, layer assignment and global bus routing. This problem was partially addressed by Kong et al. in [3] where they only focused on the layer assignment and global bus routing, assuming bus decomposition and escape routing are given. In this paper, we present an ILP-based solution to the entire bus planning problem. We apply our bus planner to an industrial PCB (with over 7000 nets and 12 signal layers) which was previously successfully routed manually, and compare with a state-of-the-art industrial internal tool where the layer assignment and global bus routing are based on the algorithm in [3]. Our bus planner successfully routed 97.4% of all the nets. This is a huge improvement over the industrial tool which could only achieve 84.7% routing completion for this board.","PeriodicalId":297528,"journal":{"name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123953665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

A low power multimedia processor implementing dynamic voltage and frequency scaling technique 一种实现动态电压和频率缩放技术的低功耗多媒体处理器

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509563

T. Enomoto, Nobuaki Kobayashi

引用次数: 1