R. Ikeno, T. Maruyama, T. Iizuka, S. Komatsu, M. Ikeda, K. Asada
{"title":"基于一维VIA阵列的高通量电子束直接写入,采用面积高效的模板设计","authors":"R. Ikeno, T. Maruyama, T. Iizuka, S. Komatsu, M. Ikeda, K. Asada","doi":"10.1109/ASPDAC.2013.6509605","DOIUrl":null,"url":null,"abstract":"Character projection (CP) is a high-speed mask-less exposure technique for electron-beam direct writing (EBDW). In CP exposure of VIA layers, higher throughput is realized if more VIAs are exposed in each EB shot, but it will result in huge number of VIA characters required for arbitrary VIA placement. We adopt one-dimensional VIA array as the basic CP character architecture to increase VIA numbers in an EB shot while saving the stencil area by superposed character arrangement. CP throughput is further improved by layout constraints for VIA placement in detail routing phase. Our experimental results give estimated EB shot counts less than 174G shot/wafer in 14nm technologies.","PeriodicalId":297528,"journal":{"name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"High-throughput electron beam direct writing of VIA layers by character projection using character sets based on one-dimensional VIA arrays with area-efficient stencil design\",\"authors\":\"R. Ikeno, T. Maruyama, T. Iizuka, S. Komatsu, M. Ikeda, K. Asada\",\"doi\":\"10.1109/ASPDAC.2013.6509605\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Character projection (CP) is a high-speed mask-less exposure technique for electron-beam direct writing (EBDW). In CP exposure of VIA layers, higher throughput is realized if more VIAs are exposed in each EB shot, but it will result in huge number of VIA characters required for arbitrary VIA placement. We adopt one-dimensional VIA array as the basic CP character architecture to increase VIA numbers in an EB shot while saving the stencil area by superposed character arrangement. CP throughput is further improved by layout constraints for VIA placement in detail routing phase. Our experimental results give estimated EB shot counts less than 174G shot/wafer in 14nm technologies.\",\"PeriodicalId\":297528,\"journal\":{\"name\":\"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)\",\"volume\":\"8 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-04-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASPDAC.2013.6509605\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASPDAC.2013.6509605","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
High-throughput electron beam direct writing of VIA layers by character projection using character sets based on one-dimensional VIA arrays with area-efficient stencil design
Character projection (CP) is a high-speed mask-less exposure technique for electron-beam direct writing (EBDW). In CP exposure of VIA layers, higher throughput is realized if more VIAs are exposed in each EB shot, but it will result in huge number of VIA characters required for arbitrary VIA placement. We adopt one-dimensional VIA array as the basic CP character architecture to increase VIA numbers in an EB shot while saving the stencil area by superposed character arrangement. CP throughput is further improved by layout constraints for VIA placement in detail routing phase. Our experimental results give estimated EB shot counts less than 174G shot/wafer in 14nm technologies.