2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)最新文献_第6页

An ultra-compact virtual source FET model for deeply-scaled devices: Parameter extraction and validation for standard cell libraries and digital circuits 用于深度缩放器件的超紧凑虚拟源场效应管模型:标准单元库和数字电路的参数提取和验证

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509649

Li Yu, O. Mysore, Lan Wei, L. Daniel, D. Antoniadis, I. Elfadel, D. Boning

{"title":"An ultra-compact virtual source FET model for deeply-scaled devices: Parameter extraction and validation for standard cell libraries and digital circuits","authors":"Li Yu, O. Mysore, Lan Wei, L. Daniel, D. Antoniadis, I. Elfadel, D. Boning","doi":"10.1109/ASPDAC.2013.6509649","DOIUrl":"https://doi.org/10.1109/ASPDAC.2013.6509649","url":null,"abstract":"In this paper, we present the first validation of the virtual source (VS) charge-based compact model for standard cell libraries and large-scale digital circuits. With only a modest number of physically meaningful parameters, the VS model accounts for the main short-channel effects in nanometer technologies. Using a novel DC and transient parameter extraction methodology, the model is verified with simulated data from a well-characterized, industrial 40-nm bulk silicon model. The VS model is used to fully characterize a standard cell library with timing comparisons showing less than 2.7% error with respect to the industrial design kit. Furthermore, a 1001-stage inverter chain and a 32-bit ripple-carry adder are employed as test cases in a vendor CAD environment to validate the use of the VS model for large-scale digital circuit applications. Parametric Vdd sweeps show that the VS model is also ready for usage in low-power design methodologies. Finally, runtime comparisons have shown that the use of the VS model results in a speedup of about 7.6×.","PeriodicalId":297528,"journal":{"name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133258997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Compiler-assisted refresh minimization for volatile STT-RAM cache 易失性STT-RAM缓存的编译器辅助刷新最小化

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509608

Qing'an Li, Jianhua Li, Liang Shi, C. Xue, Yiran Chen, Yanxiang He

引用次数: 29

Performance bound and yield analysis for analog circuits under process variations 工艺变化下模拟电路的性能界限和良率分析

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509692

Xuexin Liu, A. A. Palma-Rodriguez, S. Rodriguez-Chavez, S. Tan, E. Tlelo-Cuautle, Yici Cai

引用次数: 11

MD: Minimal path-based fault-tolerant routing in on-Chip Networks 片上网络中基于最小路径的容错路由

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509555

M. Ebrahimi, M. Daneshtalab, J. Plosila, Farhad Mehdipour

引用次数: 56

Register and thread structure optimization for GPUs gpu的寄存器和线程结构优化

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509639

Yun Liang, Zheng Cui, K. Rupnow, Deming Chen

{"title":"Register and thread structure optimization for GPUs","authors":"Yun Liang, Zheng Cui, K. Rupnow, Deming Chen","doi":"10.1109/ASPDAC.2013.6509639","DOIUrl":"https://doi.org/10.1109/ASPDAC.2013.6509639","url":null,"abstract":"GPUs are an increasingly popular implementation platform for a variety of general purpose applications from mobile and embedded devices to high performance computing. The CUDA and OpenCL parallel programming models enable easy utilization of the GPU's resources. However, tuning GPU applications' performance is a complex and labor intensive task. Software programmers employ a variety of optimization techniques to explore tradeoffs between the thread parallelism and performance of a single thread. However, prior techniques ignore register allocation, a significant factor in single thread performance and, indirectly affects the number of simultaneously active threads. In this paper, we show that joint optimization of register allocation and thread structure has great potential to significantly improve performance. However, the design space for this joint optimization can be large; therefore, we develop performance metrics appropriate for evaluation within a compiler's inner loop and efficient design space exploration techniques that use the metrics to narrow the search space. Across a range of GPU applications, we achieve average performance speedup of 1.33X (up to 1.73X) with design space exploration 355X faster than the exhaustive search.","PeriodicalId":297528,"journal":{"name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134128336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

A computational model for SAT-based verification of hardware-dependent low-level embedded system software 基于sat的硬件相关底层嵌入式系统软件验证计算模型

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509684

Bernard Schmidt, Carlos Villarraga, J. Bormann, D. Stoffel, Markus Wedler, W. Kunz

引用次数: 8

Thermal simulator of 3D-IC with modeling of anisotropic TSV conductance and microchannel entrance effects 三维集成电路热模拟器的各向异性TSV电导和微通道入口效应建模

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509643

H. Qian, Hao Liang, Chip-Hong Chang, Wei Zhang, Hao Yu

引用次数: 24

SMYLE Project: Toward high-performance, low-power computing on manycore-processor SoCs SMYLE项目:在多核处理器soc上实现高性能、低功耗计算

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509655

Koji Inoue

引用次数: 2

Over 10-times high-speed, energy efficient 3D TSV-integrated hybrid ReRAM/MLC NAND SSD by intelligent data fragmentation suppression 超过10倍高速，节能3D tsv集成混合ReRAM/MLC NAND SSD智能数据碎片抑制

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509566

Chao Sun, Hiroki Fujii, K. Miyaji, K. Johguchi, K. Higuchi, K. Takeuchi

引用次数: 9

DARNS:A randomized multi-modulo RNS architecture for double-and-add in ECC to prevent power analysis side channel attacks DARNS:一种随机多模RNS架构，用于ECC中的双加和加，以防止功率分析侧信道攻击

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509667

Jude Angelo Ambrose, H. Pettenghi, L. Sousa

引用次数: 7