2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)最新文献_第5页

Can we identify smartphone app by power trace? [Extended abstract for special session] 我们能通过电量追踪来识别智能手机应用吗?[特别会议扩展摘要]

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509624

Mian Dong, Po-Hsiang Lai, Zhu Li

引用次数: 0

A binding algorithm in high-level synthesis for path delay testability 路径延迟可测性高级综合中的绑定算法

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509653

Yuki Yoshikawa

引用次数: 1

Loadsa: A yield-driven top-down design method for STT-RAM array 一种产量驱动的STT-RAM阵列自顶向下设计方法

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509611

Wujie Wen, Yaojun Zhang, Lu Zhang, Yiran Chen

{"title":"Loadsa: A yield-driven top-down design method for STT-RAM array","authors":"Wujie Wen, Yaojun Zhang, Lu Zhang, Yiran Chen","doi":"10.1109/ASPDAC.2013.6509611","DOIUrl":"https://doi.org/10.1109/ASPDAC.2013.6509611","url":null,"abstract":"As an emerging nonvolatile memory technology, spin-transfer torque random access memory (STT-RAM) faces great design challenges. The large device variations and the thermal-induced switching randomness of the magnetic tunneling junction (MTJ) introduce the persistent and non-persistent errors in STT-RAM operations, respectively. Modeling these statistical metrics generally require the expensive Monte-Carlo simulations on the combined magnetic-CMOS models, which is hardly integrated in the modern micro-architecture and system designs. Also, the conventional bottom-up design method incurs costly iterations in the STT-RAM design toward specific system requirement. In this work, we propose Loadsa1: a yield-driven top-down design method to explore the design space of STT-RAM array from a statistical point of view. Both array-level semi-analytical yield model and cell-level failure-probability model are developed to enable a top-down design method: The system-level requirements, e.g., the chip yield under power and area constraints, are hierarchically mapped to array-and cell-level design parameters, e.g., redundancy, ECC scheme, and MOS transistor size, etc. Our simulation results show that Loadsa can accurately optimize the STT-RAM based on the system and cell-level constraints with a linear computation complexity. Our method demonstrates great potentials in the early design stage of memory or micro-architecture by eliminating the design integrations, while offering a full statistical view of the design even when the common yield enhancement practices are applied.","PeriodicalId":297528,"journal":{"name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129383959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Optimal partition with block-level parallelization in C-to-RTL synthesis for streaming applications 流应用程序C-to-RTL合成中具有块级并行化的最优分区

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509600

Shuangchen Li, Yongpan Liu, X. Hu, Xinyu He, Yining Zhang, Pei Zhang, Huazhong Yang

引用次数: 12

An efficient compression scheme for checkpointing of FPGA-based digital mockups 基于fpga的数字模型检查点的有效压缩方案

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509669

Ting-Shuo Chou, T. Givargis, Chen-Chun Huang, Bailey Miller, F. Vahid

{"title":"An efficient compression scheme for checkpointing of FPGA-based digital mockups","authors":"Ting-Shuo Chou, T. Givargis, Chen-Chun Huang, Bailey Miller, F. Vahid","doi":"10.1109/ASPDAC.2013.6509669","DOIUrl":"https://doi.org/10.1109/ASPDAC.2013.6509669","url":null,"abstract":"This paper outlines a transparent and nonintrusive checkpointing mechanism for use with FPGA-based digital mockups. A digital mockup is an executable model of a physical system and used for real-time test and validation of cyber-physical devices that interact with the physical system. These digital mockups are typically defined in terms of a large set of ordinary differential equations. We consider digital mockups impelemented on field-programmable gate arrays (FPGAs). A checkpoint is a snapshot of the internal state of the model at a specific point in time as captured by some controller that resides on the same FPGA. We require that the model continues uninterrupted execution during a checkpointing operation. Once a checkpoint is created, the corresponding state information is transferred from the FPGA to a host computer for visualization and other off-chip processing. We outline the architecture of a checkpointing controller that captures and transfers the state information at a desired clock cycle using an aggressive compression technique. Our compression technique achieves 90% reduction in data transferred from the FPGA to the host computer under periodic checkpointing scenarios. The checkpointing with compression yields 15-36% FPGA size overhead, versus 6-11% for checkpointing without compression.","PeriodicalId":297528,"journal":{"name":"2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114580027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Mobile user classification and authorization based on gesture usage recognition 基于手势使用识别的移动用户分类与授权

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509626

Kent W. Nixon, Xiang Chen, Zhihong Mao, Yiran Chen, Kang Li

引用次数: 4

Line sharing cache: Exploring cache capacity with frequent line value locality 线路共享缓存:使用频繁的线路值局部性探索缓存容量

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509677

Keitarou Oka, Hiroshi Sasaki, Koji Inoue

引用次数: 1

Equivalent circuit model extraction for interconnects in 3D ICs 三维集成电路互连等效电路模型提取

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509549

A. Engin

引用次数: 2

A flexible fixed-outline floorplanning methodology for mixed-size modules 一个灵活的固定轮廓的平面规划方法，用于混合大小的模块

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509635

Kai-Chung Chan, Chao-Jam Hsu, Jiarping Lin

引用次数: 3

A 7.5Gb/s referenceless transceiver for UHDTV with adaptive equalization and bandwidth scanning technique in 0.13µm CMOS process 采用0.13µm CMOS工艺，采用自适应均衡和带宽扫描技术的7.5Gb/s无参考UHDTV收发器

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2013-04-29 DOI: 10.1109/ASPDAC.2013.6509570

Junyoung Song, Hyun-Woo Lee, Sewook Hwang, I. Jung, Chulwoo Kim

引用次数: 0