2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)最新文献_第2页

A Runtime Fault-Tolerant Routing Scheme for Partially Connected 3D Networks-on-Chip 部分连接3D片上网络的运行时容错路由方案

2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2018-10-01 DOI: 10.1109/DFT.2018.8602971

A. Coelho, A. Charif, N. Zergainoh, R. Velazco

{"title":"A Runtime Fault-Tolerant Routing Scheme for Partially Connected 3D Networks-on-Chip","authors":"A. Coelho, A. Charif, N. Zergainoh, R. Velazco","doi":"10.1109/DFT.2018.8602971","DOIUrl":"https://doi.org/10.1109/DFT.2018.8602971","url":null,"abstract":"Three-dimensional Networks-on-Chip (3D-NoC) have emerged as an effective solution to the scalability and latency issues in modern complex System-On-Chips. Through-Silicon Via (TSV) is usually adopted as a viable technology enabling vertical connection among NoC layers. However, TSV-based architectures typically exhibit high vulnerability to transient and permanent faults, calling for robust routing solutions capable of sustaining operation under unpredictable failure patterns. In this paper, we introduce a complete routing solution that guarantees 100% packet delivery under an unconstrained set of runtime and permanent vertical link failures. This scheme features a baseline fully-connected low-latency deadlock-free routing algorithm, and a runtime mechanism to dynamically and progressively reconfigure the network without any packet loss. Simulation results demonstrate the effectiveness of our approach in terms of performance and reliability when compared with the state-of-the-art. Furthermore, the hardware synthesis performed using commercial 28nm technology library shows a reasonable area and power overhead with respect to the non-fault-tolerant baseline.","PeriodicalId":297244,"journal":{"name":"2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126500985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Evaluating the Resilience of Parallel Applications 评估并行应用程序的弹性

2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2018-10-01 DOI: 10.1109/DFT.2018.8602987

Mark Wilkening, Fritz G. Previlon, D. Kaeli, S. Gurumurthi, Steven E. Raasch, Vilas Sridharan

引用次数: 4

Performance-Based and Aging-Aware Resource Allocation for Concurrent GPU Applications 基于性能和感知老化的并发GPU应用资源分配

2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2018-10-01 DOI: 10.1109/DFT.2018.8602850

Zois-Gerasimos Tasoulas, Ryan Guss, Iraklis Anagnostopoulos

引用次数: 2

A Method to Model Statistical Path Delays for Accurate Defect Coverage 为精确的缺陷覆盖建立统计路径延迟模型的方法

2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2018-10-01 DOI: 10.1109/DFT.2018.8602962

Pavan Kumar Javvaji, S. Tragoudas

引用次数: 1

State Recovery for Coarse-Grain TMR Designs in FPGAs Using Partial Reconfiguration fpga中使用部分重构的粗粒度TMR设计状态恢复

2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2018-10-01 DOI: 10.1109/DFT.2018.8602984

Markus Schütz, A. Steininger, F. Huemer, J. Lechner

引用次数: 1

Effects of Voltage and Temperature Variations on the Electrical Masking Capability of Sub-65 nm Combinational Logic Circuits 电压和温度变化对sub - 65nm组合逻辑电路电掩蔽能力的影响

2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2018-10-01 DOI: 10.1109/DFT.2018.8602975

Semiu A. Olowogemo, W. H. Robinson, D. Limbrick

{"title":"Effects of Voltage and Temperature Variations on the Electrical Masking Capability of Sub-65 nm Combinational Logic Circuits","authors":"Semiu A. Olowogemo, W. H. Robinson, D. Limbrick","doi":"10.1109/DFT.2018.8602975","DOIUrl":"https://doi.org/10.1109/DFT.2018.8602975","url":null,"abstract":"Single Event Transients (SETs) induced from radiation strikes on an integrated circuit (IC) can be masked electrically by logic gates while propagating through the circuit towards a storage element (e.g., flip-flop). With the continuous scaling of CMOS technology, there are simultaneous reductions in voltage, cell size, and internal capacitances that impact the properties of the gates. The combined impact causes a reduction in the electrical masking capability of the gates. The reduction in electrical masking means that transients are more likely to reach the storage elements. In addition, variations in voltage and temperature could enhance the propagation of transient towards the storage elements. This paper describes the effects of temperature and voltage variations on the electrical masking of sub-65 nm combinational logic circuits. The worst-case temperature increases the SET pulsewidth by 57.6%. The worst-case voltage increases the SET pulsewidth by 51.2%. The pulses are therefore less likely to be masked electrically.","PeriodicalId":297244,"journal":{"name":"2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"361 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115935128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Fast Dynamic Device Authentication Based on Lorenz Chaotic Systems 基于Lorenz混沌系统的快速动态设备认证

2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2018-10-01 DOI: 10.1109/DFT.2018.8602986

Lake Bu, Hai Cheng, M. Kinsy

{"title":"Fast Dynamic Device Authentication Based on Lorenz Chaotic Systems","authors":"Lake Bu, Hai Cheng, M. Kinsy","doi":"10.1109/DFT.2018.8602986","DOIUrl":"https://doi.org/10.1109/DFT.2018.8602986","url":null,"abstract":"Chaotic systems, such as Lorenz systems or logistic functions, are known for their rapid divergence property. Even the smallest change in the initial condition will lead to vastly different outputs. This property renders the short-term behavior, i.e., output values, of these systems very hard to predict. Because of this divergence feature, lorenz systems are often used in cryptographic applications, particularly in key agreement protocols and encryptions. Yet, these chaotic systems do exhibit long-term deterministic behaviors-i.e., fit into a known shape over time. In this work, we propose a fast dynamic device authentication scheme that leverages both the divergence and convergence features of the Lorenz systems. In the scheme, a device proves its legitimacy by showing authentication tags belonging to a predetermined trajectory of a given Lorenz chaotic system. The security of the proposed technique resides in the fact that the short-range function output values are hard for an attacker to predict, but easy for a verifier to validate because the function is deterministic. In addition, in a multi-verifier scenario such as a mobile phone switching among base stations, the device does not have to re-initiate a separate authentication procedure each time. Instead, it just needs to prove the consistency of its chaotic behavior in an iterative manner, making the procedure very efficient in terms of execution time and computing resources.","PeriodicalId":297244,"journal":{"name":"2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116980197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Postprocessing Procedure for Reducing the Faulty Switching Activity of a Low-Power Test Set 降低低功耗测试集故障切换活动的后处理程序

2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2018-10-01 DOI: 10.1109/DFT.2018.8602967

I. Pomeranz

引用次数: 1

Multiple Fault Detection in Nano Programmable Logic Arrays 纳米可编程逻辑阵列的多重故障检测

2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2018-10-01 DOI: 10.1109/DFT.2018.8602985

P. Junsangsri, F. Lombardi

{"title":"Multiple Fault Detection in Nano Programmable Logic Arrays","authors":"P. Junsangsri, F. Lombardi","doi":"10.1109/DFT.2018.8602985","DOIUrl":"https://doi.org/10.1109/DFT.2018.8602985","url":null,"abstract":"This paper presents a new method for testing on a go-nogo basis nano programmable logic arrays; the basic configuration of an array made of passive and active interconnect resources (lines and switches) on two connected planes (AND and OR) is analyzed under a comprehensive multiple fault model. This model is applicable to production testing at nano manufacturing and considers faults (such as stuck-at and bridging faults) in the passive interconnect line structure as well as programming faults in the active resources (switching or crosspoint faults). The proposed method achieves full coverage in fault detection by configuring the array multiple times using a four-step procedure; as the complexity of testing such chip is largely dependent on the number of configuration rounds (also often referred to as programming phases) that the chip must undergo, then at production the proposed method achieves a substantial reduction in test time compared with previous techniques. Different from previous techniques that have a complexity as function of array size (i.e. quadratic with the dimension of the planes in the array), it is shown that the proposed technique has a complexity linear with the largest dimension of a plane in the nano array. Simulation results are provided to show that 100% detection is achieved and for detection, the average number of configuration rounds is significantly less than the upper bound predicted by the presented theory.","PeriodicalId":297244,"journal":{"name":"2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126658951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

MATS**: An On-Line Testing Approach for Reconfigurable Embedded Memories MATS**:可重构嵌入式存储器的在线测试方法

2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) Pub Date : 2018-10-01 DOI: 10.1109/DFT.2018.8602934

Ludovica Bozzoli, L. Sterpone

{"title":"MATS**: An On-Line Testing Approach for Reconfigurable Embedded Memories","authors":"Ludovica Bozzoli, L. Sterpone","doi":"10.1109/DFT.2018.8602934","DOIUrl":"https://doi.org/10.1109/DFT.2018.8602934","url":null,"abstract":"Modern Field Programmable Gate Arrays (FPGAs) embed dedicated blocks for Memories (BRAMs), digital signal processing (DSPs) and hardwired microprocessors merged with the reconfigurable logic array. This trend, coupled with Error Correction Code (ECC) mechanism and Dynamic Partial Reconfiguration (DPR), makes these devices ideal candidates for mission critical applications where high reliability is a strict requirement. Therefore, efficient and in-field testing became a major concern. Unfortunately, typical on-line memory testing approaches are not fully optimized for the reconfigurable scenario. In fact, a suitable fault model should be considered in order to enhance the fault coverage and reduce the test redundancy. In this work, we proposed the MATS** algorithm, which is able to reduce the execution time and optimize the fault coverage with respect to most popular embedded memories March Tests. Furthermore, MATS** results to be highly suitable to be executed, even partially, in brief time slots available within the device mission. Experimental results show that our approach is around 30% faster than state-of-the-art solutions while achieving the optimal fault coverage.","PeriodicalId":297244,"journal":{"name":"2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"502 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131479558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3