Effects of Voltage and Temperature Variations on the Electrical Masking Capability of Sub-65 nm Combinational Logic Circuits

Abstract

Single Event Transients (SETs) induced from radiation strikes on an integrated circuit (IC) can be masked electrically by logic gates while propagating through the circuit towards a storage element (e.g., flip-flop). With the continuous scaling of CMOS technology, there are simultaneous reductions in voltage, cell size, and internal capacitances that impact the properties of the gates. The combined impact causes a reduction in the electrical masking capability of the gates. The reduction in electrical masking means that transients are more likely to reach the storage elements. In addition, variations in voltage and temperature could enhance the propagation of transient towards the storage elements. This paper describes the effects of temperature and voltage variations on the electrical masking of sub-65 nm combinational logic circuits. The worst-case temperature increases the SET pulsewidth by 57.6%. The worst-case voltage increases the SET pulsewidth by 51.2%. The pulses are therefore less likely to be masked electrically.