2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS)最新文献

筛选
英文 中文
4b/4b/8b Precision Charge-Domain 8T-SRAM Based CiM for CNN Processing 基于4b/4b/8b精密电荷域8T-SRAM的CiM用于CNN处理
Qibang Zang, W. Goh, Y. Chong, A. Do
{"title":"4b/4b/8b Precision Charge-Domain 8T-SRAM Based CiM for CNN Processing","authors":"Qibang Zang, W. Goh, Y. Chong, A. Do","doi":"10.1109/AICAS57966.2023.10168593","DOIUrl":"https://doi.org/10.1109/AICAS57966.2023.10168593","url":null,"abstract":"Compute-in-memory (CiM) is a promising solution for solving the bottleneck of frequent data movement between the memory and processor in Von-Neumann architecture. In conventional multi-bit CiM architecture, when computing N-bit input and N-bit weight MAC operation, 2N 1 cycles are needed for N-bit input modulation and normally 3-4−cycles with complex switch operation are needed for N-bit weight realization, which significantly degrades the final throughput and power efficiency. In this work, a C-2C DAC built in the 8T SRAM CiM array is designed for 4-bit weight and 4-bit input MAC operation, which can be completed in just one cycle. In the final power efficiency evaluation, our 4b/4b/8b CiM architecture attained up to 640 TOPS/W (normalized to 1b/1b/1b precision) which is a 6-10 times improvement as compared to the conventional multi-bit CiM architectures. The proposed architecture with 4b/4b/8b precision can provide 91.47% and 68.10% accuracy on CIFAR-10 and CIFAR-100 dataset classification, respectively.","PeriodicalId":296649,"journal":{"name":"2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS)","volume":"183 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133156224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Deep-learning-based X-ray CT Slice Analysis for Layout Verification in Printed Circuit Boards 基于深度学习的印刷电路板布局验证x射线CT切片分析
Deruo Cheng, Yiqiong Shi, Yee-Yang Tee, Jingsi Song, Xue Wang, B. Wen, B. Gwee
{"title":"Deep-learning-based X-ray CT Slice Analysis for Layout Verification in Printed Circuit Boards","authors":"Deruo Cheng, Yiqiong Shi, Yee-Yang Tee, Jingsi Song, Xue Wang, B. Wen, B. Gwee","doi":"10.1109/AICAS57966.2023.10168608","DOIUrl":"https://doi.org/10.1109/AICAS57966.2023.10168608","url":null,"abstract":"3D X-ray Computational Tomography (CT) systems have been employed to inspect Printed Circuit Boards (PCB) for security analysis, considering the heightened trustworthiness concern on the globalized supply chain. In this paper, we propose a deep-learning-based layout verification (DELVer) framework to automatically extract PCB layout information from X-ray CT slices and verify against the design files. Leveraging on geometrical projective transformation, our proposed DELVer framework aligns the acquired CT slice of each PCB layer with their corresponding design file, to train state-of-the-art deep learning models for layout extraction and verification. It thus alleviates the laborious manual data labeling for deep learning models. With a cross-device evaluation on 4 multi-layer satellite PCBs of board size around 90 cm2, our proposed DELVer framework demonstrates how deep learning models can generalize to unseen target PCBs for layout verification, establishing an efficient solution for PCB assurance and industrial failure analysis.","PeriodicalId":296649,"journal":{"name":"2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116541201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Modified Logarithmic Multiplication Approximation for Machine Learning 机器学习的修正对数乘法近似
I. Kouretas, Vassilis Paliouras, T. Stouraitis
{"title":"Modified Logarithmic Multiplication Approximation for Machine Learning","authors":"I. Kouretas, Vassilis Paliouras, T. Stouraitis","doi":"10.1109/AICAS57966.2023.10168664","DOIUrl":"https://doi.org/10.1109/AICAS57966.2023.10168664","url":null,"abstract":"In this paper, a novel approximation that allows exploitation of the full potential of logarithmic multiplication is proposed. More specifically, the proposed approximation is quantified in terms of mean square error (MSE) and compared to a competitive recent publication. Subsequently, an LSTM network is used as an illustrative test case and the proposed approximation is validated in terms of the accuracy of the netowrk. It has been shown that for short data wordlengths, the proposed approximation can achieve small loss values, for the particular LSTM network. Finally, the circuit implementation of the logarithmic multiplier is synthesized in a 28 nm standard-cell library. Results show reduced hardware complexity for similar loss values on the specific LSTM network.","PeriodicalId":296649,"journal":{"name":"2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123888790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Binary is All You Need: Ultra-Efficient Arrhythmia Detection with a Binary-Only Compressive System 二进制是所有你需要的:超高效的心律失常检测与二进制压缩系统
Fengshi Tian, Xiaomeng Wang, Jinbo Chen, Jie Yang, M. Sawan, C. Tsui, Kwang-Ting Cheng
{"title":"Binary is All You Need: Ultra-Efficient Arrhythmia Detection with a Binary-Only Compressive System","authors":"Fengshi Tian, Xiaomeng Wang, Jinbo Chen, Jie Yang, M. Sawan, C. Tsui, Kwang-Ting Cheng","doi":"10.1109/AICAS57966.2023.10168576","DOIUrl":"https://doi.org/10.1109/AICAS57966.2023.10168576","url":null,"abstract":"Detecting cardiac arrhythmia is critical for preventing heart attacks, and wearable electrocardiograph (ECG) systems have been developed to address this issue. However, the energy consumption of existing wearable systems is still significant at both the circuit and system levels, posing a challenge for their design. In this paper, we propose a novel ultra-efficient binary-only compressive ECG system for edge cardiac arrhythmia detection, featuring an event-driven level-crossing analog-to-spike converter (ATS) for sensing and a computing-in-memory (CIM) based binarized neural network (BNN) processor for compressive processing. Through system-level co-design, our proposed system achieves high arrhythmia detection accuracy and ultra-low energy consumption. Our simulations using the MIT-BIH dataset show that the proposed system achieves a 90.1% reduction in sampled data points compared to Nyquist sampling. Moreover, our dedicated BNN on a CIM engine delivers 97.03% arrhythmia detection accuracy with energy efficiency as low as 0.17uJ/inference.","PeriodicalId":296649,"journal":{"name":"2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126436519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Energy Efficient Software-hardware Co-design of Quantized Recurrent Convolutional Neural Network for Continuous Cardiac Monitoring 用于心脏连续监测的量化循环卷积神经网络节能软硬件协同设计
Jinhai Hu, Cong Sheng Leow, W. Goh, Yuan Gao
{"title":"Energy Efficient Software-hardware Co-design of Quantized Recurrent Convolutional Neural Network for Continuous Cardiac Monitoring","authors":"Jinhai Hu, Cong Sheng Leow, W. Goh, Yuan Gao","doi":"10.1109/AICAS57966.2023.10168601","DOIUrl":"https://doi.org/10.1109/AICAS57966.2023.10168601","url":null,"abstract":"This paper presents an electrocardiogram (ECG) signal classification model based on Recurrent Convolutional Neural Network (RCNN). With recurrent connections and data buffers, a single convolutional layer is reused to implement multiple layers function. Using a 5-layers CNN network as an example, this approach reduces the number of parameters by more than 50% while achieving the same feature extraction size. Furthermore, quantized RCNN (QRCNN) is proposed where the input signal, interlayer output, and kernel weights are quantized to unsigned INT8, INT4, and signed INT4 respectively. For hardware implementation, pipelining and data reuse within the 1-D convolution kernel can potentially reduce latency. QRCNN model achieved 98.08% validation accuracy on MIT-BIH datasets with only 1% degradation due to quantization. The estimated dynamic power consumption of the QRCNN is less than 60% of a conventional quantized CNN when implemented on a Xilinx Artix-7 FPGA, showing the potential for resource-constraint edge devices.","PeriodicalId":296649,"journal":{"name":"2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122393487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Efficient Algorithms for Accelerating Spiking Neural Networks on MAC Array of SpiNNaker 2 SpiNNaker MAC阵列上加速尖峰神经网络的高效算法
Jiaxin Huang, Florian Kelber, B. Vogginger, Binyi Wu, Felix Kreutz, Pascal Gerhards, Daniel Scholz, Klaus Knobloch, C. Mayr
{"title":"Efficient Algorithms for Accelerating Spiking Neural Networks on MAC Array of SpiNNaker 2","authors":"Jiaxin Huang, Florian Kelber, B. Vogginger, Binyi Wu, Felix Kreutz, Pascal Gerhards, Daniel Scholz, Klaus Knobloch, C. Mayr","doi":"10.1109/AICAS57966.2023.10168559","DOIUrl":"https://doi.org/10.1109/AICAS57966.2023.10168559","url":null,"abstract":"The CPU-based system is widely used for simulating the brain-inspired spiking neural networks (SNN) by taking the benefit of flexibility, while processing high input spiking rates caused by immature coding mechanism costs many CPU cycles, and the introduction of additional information required by serial execution needs the time-consuming pre- and post-neuron matching algorithm. To address these issues, we propose an algorithm set leveraging the multiply-accumulate (MAC) array to accelerate the SNN inference. By rearranging and compressing operands losslessly, we retain the advantage of the MAC array on fast parallel computing, as well as alleviate the ineffective memory occupation and the waste of computing resources, which result from the inherent sparse feature of SNN and reluctant memory alignment from fixed MAC hardware structure. Benchmarking with an SNN radar gesture recognition model, the algorithms jointly optimize 82.71% of the execution time compared to the serial computation on the ARM M4F of the SpiNNaker 2 chip; 49.89% of the memory footprint is reduced contrasted with the unoptimized MAC calculation. This article explicitly expands the application field of the General Sparse Matrix-Matrix Multiplication (SpGEMM) issue to SNN, developing novel SpGEMM optimization algorithms fitting the SNN feature and MAC array.","PeriodicalId":296649,"journal":{"name":"2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121198381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Live Demonstration: Real-time Analyses of Biosignals based on a Dedicated CMOS Configurable Deep Learning Engine 现场演示:基于专用CMOS可配置深度学习引擎的生物信号实时分析
Junzhe Wang, Shiqi Zhao, Chaoming Fang, Jie Yang, M. Sawan
{"title":"Live Demonstration: Real-time Analyses of Biosignals based on a Dedicated CMOS Configurable Deep Learning Engine","authors":"Junzhe Wang, Shiqi Zhao, Chaoming Fang, Jie Yang, M. Sawan","doi":"10.1109/AICAS57966.2023.10168631","DOIUrl":"https://doi.org/10.1109/AICAS57966.2023.10168631","url":null,"abstract":"Biosignals generated by human bodies contain valuable information about a person’s physical or psychological states. In recent years, machine-learning algorithms have significantly increased the accuracy and usefulness of biosignal analysis in areas such as disease diagnoses and treatments. To make these analyses more portable and accessible, we have designed and fabricated a dedicated processor named CODE, which supports machine-learning processing of various types of biosignals, including electroencephalography (EEG), electromyography (EMG), and electrocardiography (ECG), with high power efficiency and low latency. In this demonstration, we will show how the CODE chip processes biosignal data in real-time and show measurements of its power consumption and efficiency.","PeriodicalId":296649,"journal":{"name":"2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124361062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Convolved Self-Attention Model for IMU-based Gait Detection and Human Activity Recognition 基于imu的步态检测和人体活动识别的卷积自注意模型
Shuailin Tao, W. Goh, Yuan Gao
{"title":"A Convolved Self-Attention Model for IMU-based Gait Detection and Human Activity Recognition","authors":"Shuailin Tao, W. Goh, Yuan Gao","doi":"10.1109/AICAS57966.2023.10168654","DOIUrl":"https://doi.org/10.1109/AICAS57966.2023.10168654","url":null,"abstract":"This paper presents a convolved self-attention neural network model for gait detection and human activity recognition (HAR) tasks using wearable inertial measurement unit (IMU) sensors. By embedding a convolved window inside the self-attention module, prior time step knowledge is utilized by self-attention layer to improve accuracy. Moreover, a streamlined fully connected (FC) layer without hidden layers is proposed for the feature mixer. This arrangement enables significant reduction of overall network parameters, since hidden layers occupy the majority of the parameters in a transformer encoder. Compared to the other state-of-art neural networks, the proposed method achieved better accuracy of 95.83% and 96.01% with the smallest network size on HAR datasets UCI-HAR and MHEALTH respectively,","PeriodicalId":296649,"journal":{"name":"2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS)","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131725053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Ternary Weight Mapping and Charge-mode Readout Scheme for Energy Efficient FeRAM Crossbar Compute-in-Memory System 一种高能效FeRAM跨栏内存计算系统的三元权映射和电荷模式读出方案
T. Cao, Zhongyi Zhang, W. Goh, Chen Liu, Yao Zhu, Yuan Gao
{"title":"A Ternary Weight Mapping and Charge-mode Readout Scheme for Energy Efficient FeRAM Crossbar Compute-in-Memory System","authors":"T. Cao, Zhongyi Zhang, W. Goh, Chen Liu, Yao Zhu, Yuan Gao","doi":"10.1109/AICAS57966.2023.10168639","DOIUrl":"https://doi.org/10.1109/AICAS57966.2023.10168639","url":null,"abstract":"This work presents an edge-AI system built on capacitive ferroelectric random-access memory (FeRAM) crossbar array, which is compatible with CMOS backend-of-line (BEOL) fabrication process. A novel capacitive crossbar circuit and a ternary mapping technique are proposed. Compared to the conventional binary representation, the proposed ternary mapping improves the storage efficiency exponentially in weight resolution. The feasibility of neuromorphic computing system implemented on FeRAM crossbar array is explored with speech command classification task. A ResNet-32 model with 0.45M parameters is implemented on 64 × 64 FeRAM crossbar array with the measured FeRAM model. It achieved 97.12% inference accuracy with 2 ternary digits and 5% device variation on Google Speech Command dataset 35-command classification task.","PeriodicalId":296649,"journal":{"name":"2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS)","volume":"2015 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134060351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
PPT-KP: Pruning Point Training-based Kernel Pruning for Deep Convolutional Neural Networks 基于剪枝点训练的深度卷积神经网络核剪枝
Kwanghyun Koo, Hyun Kim
{"title":"PPT-KP: Pruning Point Training-based Kernel Pruning for Deep Convolutional Neural Networks","authors":"Kwanghyun Koo, Hyun Kim","doi":"10.1109/AICAS57966.2023.10168622","DOIUrl":"https://doi.org/10.1109/AICAS57966.2023.10168622","url":null,"abstract":"Pruning, which is a representative method for compressing huge convolutional neural network (CNN) models, has been mainly studied in two directions: weight pruning and filter pruning, with both approaches having clear limitations caused by their intrinsic characteristics. To solve this problem, research on kernel pruning, which has the advantages of both methods, has recently advanced. In this study, pruning point training-based kernel pruning (PPT-KP) is proposed to address the problems of existing kernel pruning methods. With PPT-KP, the L1 norm of the kernel converges to zero through an adaptive regularizer that applies L1 regularization of different intensities depending on the size of the L1 norm of the kernel to secure network sparsity and obtain multiple margin spaces for pruning. Thus, outstanding kernel pruning is possible because several pruning points can be created. PPT-KP outperformed several existing filter pruning and kernel pruning methods on various networks and datasets in terms of the trade-off between FLOPs reduction and accuracy drops. In particular, PPT-KP reduced parameters and FLOPs by 77.2% and 68.9%, respectively, in ResNet-56 on the CIFAR-10 dataset with only a 0.05% accuracy degradation.","PeriodicalId":296649,"journal":{"name":"2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133447360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信